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HT66F60 Datasheet(PDF) 28 Page - Holtek Semiconductor Inc |
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HT66F60 Datasheet(HTML) 28 Page - Holtek Semiconductor Inc |
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28 / 298 page ![]() Rev. 1.90 �8 �e���a�� 18� �01� Rev. 1.90 �9 �e���a�� 18� �01� HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type 8-Bit MCU with EEPROM HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type 8-Bit MCU with EEPROM System Architecture Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed totheirinternalsystemarchitecture.Therangeofdevicestakeadvantageoftheusualfeaturesfound withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance. Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionset operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement, branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulator andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea functionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthe devicesuitableforlow-cost,high-volumeproductionforcontrollerapplications. Clocking and Pipelining Themainsystemclock,derivedfromeitheraHXT,LXT,HIRC,LIRCorERCoscillatoris subdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounteris incrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.The remainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4 clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakes placeinconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthat instructionsareeffectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructions wherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhich casetheinstructionwilltakeonemoreinstructioncycletoexecute. Fe tc h In st . ( PC ) Ex ec ut e In st . (P C- 1) Fe tc h In st . (P C+ 1) Ex ec ut e In st . (P C) Fe tc h In st . (P C+ 2) Ex ec ut e In st . (P C+ 1) PC PC +1 PC +2 f SY S (S yst em C lo ck) P has e Cl o ck T1 Pr ogr am C oun te r P has e Cl o ck T2 P has e Cl o ck T3 P has e Cl o ck T4 Pi pe lin in g System Clocking and Pipelining |
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