AM3359 datasheet(114/236 Pages) TI

114 / 236 page

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

SPRS717F – OCTOBER 2011 – REVISED APRIL 2013

www.ti.com

4.2.3

Output Clock Specifications

The AM335x device has two clock output signals. The CLKOUT1 signal is always a replica of the OSC0

input clock which is referred to as the master oscillator (CLK_M_OSC) in the AM335x ARM Cortex-A8

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). The CLKOUT2

signal can be configured to output the OSC1 input clock, which is referred to as the 32K oscillator

(CLK_32K_RTC) in the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual

(literature number SPRUH73), or four other internal clocks. For more information related to configuring

these clock output signals, see the CLKOUT Signals section of the AM335x ARM Cortex-A8

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).

4.2.4

Output Clock Characteristics

NOTE

The AM335x CLKOUT1 and CLKOUT2 clock outputs should not be used as a synchronous

clock for any of the peripheral interfaces because they were not timing closed to any other

signals. These clock outputs also were not designed to source any time critical external

circuits that require a low jitter reference clock. The jitter performance of these outputs is

unpredictable due to complex combinations of many system variables. For example,

CLKOUT2 may be sourced from several PLLs with each PLL supporting many configurations

that yield different jitter performance. There are also other unpredictable contributors to jitter

performance such as application specific noise or crosstalk into the clock circuits. Therefore,

there are no plans to specify jitter performance for these outputs.

4.2.4.1

CLKOUT1

The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one

of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must be

configured for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal.

The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level

applied to the LCD_DATA5 terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0

multiplexer is configured to Mode 7 if the LCD_DATA5 terminal is low on the rising edge of PWRONRSTn

or Mode 3 if the LCD_DATA5 terminal is high on the rising edge of PWRONRSTn. This allows the

CLKOUT1 signal to be output on the XDMA_EVENT_INTR0 terminal without software intervention. In this

mode, the output is held low while PWRONRSTn is active and begins to toggle after PWRONRSTn is

released.

4.2.4.2

CLKOUT2

The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one

of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must be

configured for Mode 3 to connect the CLKOUT2 signal to the XDMA_EVENT_INTR1 terminal.

The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must

configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the

XDMA_EVENT_INTR1 terminal.

114

Power and Clocking

Submit Documentation Feedback

Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352

AM3359 Datasheet(PDF) 114 Page - Texas Instruments

AM3359 Datasheet(HTML) 114 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL