AM3359 datasheet(157/236 Pages) TI

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AM335x

DQ[0]

DQ[1]

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717F – OCTOBER 2011 – REVISED APRIL 2013

Figure 5-37 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to

point. Skew matching across bytes is not needed nor recommended.

Figure 5-37. DQS[x] and DQ[x] Routing and Topology

Table 5-42. DQS[x] and DQ[x] Routing Specification(1)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

Center-to-center DQS[x] spacing

Center-to-center DDR_DQS[x] to other LPDDR trace spacing(2)

DQS[x] and DQ[x] nominal trace length(3)

DQLM-50

DQLM

DQLM+50

mils

DQ[x]-to-DQS[x] skew length mismatch(3)

100

mils

DQ[x]-to-DQ[x] skew length mismatch(3)

100

mils

Center-to-center DQ[x] to other LPDDR trace spacing(2)(4)

Center-to-center DQ[x] to other DQ[x] trace spacing(2)(5)

(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.

(2) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3) There is no requirement for skew matching between data bytes; that is, from net classes DQS0 and DQ0 to net classes DQS1 and DQ1.

(4) Signals from one DQ net class should be considered other LPDDR traces to another DQ net class.

(5) DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.

Peripheral Information and Timings

157

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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352

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