AM3359 datasheet(161/236 Pages) TI

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AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

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SPRS717F – OCTOBER 2011 – REVISED APRIL 2013

5.6.2.2.2.2 Compatible JEDEC DDR2 Devices

Table 5-44 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.

Generally, the DDR2 interface is compatible with x16 or x8 DDR2-533 speed grade DDR2 devices.

Table 5-44. Compatible JEDEC DDR2 Devices (Per Interface)(1)

NO.

PARAMETER

MIN

MAX

UNIT

JEDEC DDR2 device speed grade(2)

DDR2-533

JEDEC DDR2 device bit width

x16

Bits

JEDEC DDR2 device count

Devices

JEDEC DDR2 device terminal count(3)

Terminals

(1) If the DDR2 interface is operated with a clock frequency less than 266 MHz, lower-speed grade DDR2 devices may be used if the

minimum clock period specified for the DDR2 device is less than or equal to the minimum clock period selected for the AM335x DDR2

interface.

(2) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.

(3) 92-terminal devices are also supported for legacy reasons. New designs will migrate to 84-terminal DDR2 devices. Electrically, the 92-

and 84-terminal DDR2 devices are the same.

5.6.2.2.2.3 PCB Stackup

The minimum stackup required for routing the AM335x device is a four-layer stackup as shown in Table 5-

45. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal

integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.

Table 5-45. Minimum PCB Stackup(1)

LAYER

TYPE

DESCRIPTION

Signal

Top signal routing

Plane

Ground

Plane

Split Power Plane

Signal

Bottom signal routing

(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these

signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in

the power plane.

Peripheral Information and Timings

161

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