OP196 datasheet(46/88 Pages) AD

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ADuC841/ADuC842/ADuC843

Rev. 0 | Page 46 of 88

SPICON SPI Control Register

SFR Address

F8H

Power-On Default

04H

Bit Addressable

Yes

Table 18. SPICON SFR Bit Designations

Bit No.

Name

Description

ISPI

SPI Interrupt Bit.

Set by the MicroConverter at the end of each SPI transfer.

Cleared directly by user code or indirectly by reading the SPIDAT SFR.

WCOL

Write Collision Error Bit.

Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress.

Cleared by user code.

SPE

SPI Interface Enable Bit.

Set by the user to enable the SPI interface.

Cleared by the user to enable the I2C pins, this is not requiredto enable the I2C interface if the MSPI bit is set in

CFG841/CFG842. In this case, the I2C interface is automatically enabled.

SPIM

SPI Master/Slave Mode Select Bit.

Set by the user to enable master mode operation (SCLOCK is an output).

Cleared by the user to enable slave mode operation (SCLOCK is an input).

CPOL1

Clock Polarity Select Bit.

Set by the user if SCLOCK idles high.

Cleared by the user if SCLOCK idles low.

CPHA1

Clock Phase Select Bit.

Set by the user if leading SCLOCK edge is to transmit data.

Cleared by the user if trailing SCLOCK edge is to transmit data.

SPR1

SPI Bit Rate Select Bits.

SPR0

These bits select the SCLOCK rate (bit rate) in master mode as follows:

SPR1

SPR0

Selected Bit Rate

fOSC/2

fOSC/4

fOSC/8

fOSC/16

In SPI slave mode, i.e., SPIM = 0, the logic level on the external SS pin can be read via the SPR0 bit.

1The CPOL and CPHA bits should both contain the same values for master and slave devices.

SPIDAT

SPI Data Register

Function

SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to

read data just received by the SPI interface.

SFR Address

F7H

Power-On Default

00H

Bit Addressable

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