OP196 datasheet(74/88 Pages) AD

74 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 74 of 88

Power Consumption

The currents consumed by the various sections of the part are

shown in Table 40. The core values given represent the current

drawn by DVDD, while the rest (ADC, DAC, voltage ref) are

pulled by the AVDD pin and can be disabled in software when

not in use. The other on-chip peripherals (such as the watchdog

timer and the power supply monitor) consume negligible

current, and are therefore lumped in with the core operating

current here. Of course, the user must add any currents sourced

by the parallel and serial I/O pins, and sourced by the DAC, in

order to determine the total current needed at the supply pins.

Also, current drawn from the DVDD supply increases by approxi-

mately 10 mA during Flash/EE erase and program cycles.

Table 40. Typical IDD of Core and Peripherals

VDD = 5 V

VDD = 3 V

Core(Normal Mode)

(2.2 nA

× MCLK)

(1.4 nA

× MCLK)

ADC

1.7 mA

DAC (Each)

250 µA

200 µA

Voltage Ref

200 µA

150 µA

Since operating DVDD current is primarily a function of clock

speed, the expressions for core supply current in Table 40 are

given as functions of MCLK, the core clock frequency. Plug in a

value for MCLK in hertz to determine the current consumed by

the core at that oscillator frequency. Since the ADC and DACs

can be enabled or disabled in software, add only the currents

from the peripherals you expect to use. And again, do not forget

to include current sourced by I/O pins, serial port pins, DAC

outputs, and so forth, plus the additional current drawn during

Flash/EE erase and program cycles. A software switch allows the

chip to be switched from normal mode into idle mode, and also

into full power-down mode. Brief descriptions of idle and

power-down modes follow.

Power Saving Modes

In idle mode, the oscillator continues to run, but the core clock

generated from the PLL is halted. The on-chip peripherals

continue to receive the clock, and remain functional. The CPU

status is preserved with the stack pointer and program counter,

and all other internal registers maintain their data during idle

mode. Port pins and DAC output pins retain their states in this

mode. The chip recovers from idle mode upon receiving any

enabled interrupt, or upon receiving a hardware reset.

In full power-down mode, both the PLL and the clock to the

core are stopped. The on-chip oscillator can be halted or can

continue to oscillate, depending on the state of the oscillator

power-down bit in the PLLCON SFR. The TIC, being driven

directly from the oscillator, can also be enabled during power-

down. All other on-chip peripherals are, however, shut down.

Port pins retain their logic levels in this mode, but the DAC

output goes to a high impedance state (three-state). During full

power-down mode, the part consumes a total of approximately

20 µA. There are five ways of terminating power-down mode:

Asserting the RESET Pin (Pin 15)

Returns to normal mode. All registers are set to their default

state and program execution starts at the reset vector once the

RESET pin is de-asserted.

Cycling Power

All registers are set to their default state and program execution

starts at the reset vector approximately 128 ms later.

Time Interval Counter (TIC) Interrupt

Power-down mode is terminated, and the CPU services the TIC

interrupt. The RETI at the end of the TIC ISR returns the core

to the instruction after the one that enabled power-down.

I2C or SPI Interrupt

Power-down mode is terminated, and the CPU services the

I2C/SPI interrupt. The RETI at the end of the ISR returns the

core to the instruction after the one that enabled power-down.

Note that the I2C/SPI power-down interrupt enable bit (SERIPD)

in the PCON SFR must be set to allow this mode of operation.

INT0 Interrupt

Power-down mode is terminated, and the CPU services the

INT0 interrupt. The RETI at the end of the ISR returns the core

to the instruction after the one that enabled power-down. The

INT0 pin must not be driven low during or within two machine

cycles of the instruction that initiates power-down mode. Note

that the INT0 power-down interrupt enable bit (INT0PD) in

the PCON SFR must be set to allow this mode of operation.

Power-On Reset (POR)

An internal POR is implemented on the ADuC841/ADuC842/

ADuC843.

3 V Part

For DVDD below 2.45 V, the internal POR holds the part in reset.

As DVDD rises above 2.45 V, an internal timer times out for

approximately 128 ms before the part is released from reset. The

user must ensure that the power supply has reached a stable

2.7 V minimum level by this time. Likewise on power-down, the

internal POR holds the part in reset until the power supply has

dropped below 1 V. Figure 82 illustrates the operation of the

internal POR in detail.

128ms TYP

1.0V TYP

128ms TYP

2.45V TYP

1.0V TYP

INTERNAL

CORE RESET

DVDD

Figure 82. Internal POR Operation

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