OP196 datasheet(73/88 Pages) AD

73 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 73 of 88

If access to more than 64 kBytes of RAM is desired, a feature

unique to the ADuC841/ADuC842/ADuC843 allows address-

ing up to 16 MBytes of external RAM simply by adding an

additional latch as illustrated in Figure 79.

LATCH

ALE

LATCH

SRAM

A8–A15

A0–A7

D0–D7

(DATA)

A16–A23

ADuC841/

ADuC842/

ADuC843

Figure 79. External Data Memory Interface (16 MBytes Address Space)

In either implementation, Port 0 (P0) serves as a multiplexed

address/data bus. It emits the low byte of the data pointer (DPL)

as an address, which is latched by a pulse of ALE prior to data

being placed on the bus by the ADuC841/ADuC842/ADuC843

(write operation) or by the SRAM (read operation). Port 2 (P2)

provides the data pointer page byte (DPP) to be latched by ALE,

followed by the data pointer high byte (DPH). If no latch is

connected to P2, DPP is ignored by the SRAM, and the 8051

standard of 64 kBytes external data memory access is maintained.

Power Supplies

The operational power supply voltage of the parts depends on

whether the part is the 3 V version or the 5 V version. The

specifications are given for power supplies within 2.7 V to 3.6 V

or ±5% of the nominal 5 V level.

Note that Figure 80 and Figure 81 refer to the PQFP package.

For the CSP package, connect the extra DVDD, DGND, AVDD,

and AGND in the same manner. Also, the paddle on the bottom

of the package should be soldered to a metal plate to provide

mechanical stability. This metal plate should not be connected

to ground.

Separate analog and digital power supply pins (AVDD and DVDD,

respectively) allow AVDD to be kept relatively free of the noisy

digital signals that are often present on the system DVDD line.

However, though you can power AVDD and DVDD from two

separate supplies if desired, you must ensure that they remain

within ±0.3 V of one another at all times to avoid damaging the

chip (as per the Absolute Maximum Ratings section). Therefore,

it is recommended that unless AVDD and DVDD are connected

directly together, back-to-back Schottky diodes should be con-

nected between them, as shown in Figure 80.

DVDD

AGND

AVDD

–

0.1

µF

ANALOG SUPPLY

µF

DGND

0.1

µF

DIGITAL SUPPLY

–

ADuC841/

ADuC842/

ADuC843

Figure 80. External Dual-Supply Connections

As an alternative to providing two separate power supplies, the

user can help keep AVDD quiet by placing a small series resistor

and/or ferrite bead between it and DVDD, and then decoupling

AVDD separately to ground. An example of this configuration is

shown in Figure 81. With this configuration, other analog

circuitry (such as op amps and voltage reference) can be powered

from the AVDD supply line as well. The user will still want to

include back-to-back Schottky diodes between AVDD and DVDD

to protect them from power-up and power-down transient

conditions that could momentarily separate the two supply voltages.

DVDD

AGND

AVDD

DGND

DIGITAL SUPPLY

–

BEAD

1.6

Ω

0.1

µF

0.1

µF

ADuC841/

ADuC842/

ADuC843

Figure 81. External Single-Supply Connections

Notice that in both Figure 80 and Figure 81, a large value

(10 µF) reservoir capacitor sits on DVDD and a separate 10 µF

capacitor sits on AVDD. Also, local small-value (0.1 µF) capaci-

tors are located at each VDD pin of the chip. As per standard

design practice, be sure to include all of these capacitors, and

ensure the smaller capacitors are close to each AVDD pin with

trace lengths as short as possible. Connect the ground terminal

of each of these capacitors directly to the underlying ground

plane. Finally, note that at all times, the analog and digital ground

pins on the part must be referenced to the same system ground

reference point.

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