OP196 datasheet(59/88 Pages) AD

59 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 59 of 88

MOSI is shared with P3.3 and, as such, has the same

configuration as the one shown in Figure 61.

MCO

I2C M

SCLOCK

(OFF)

DVDD

50ns GLITCH

REJECTION FILTER

SPE = 0 (I2C ENABLE)

HARDWARE I2C

(SLAVE ONLY)

SFR

BITS

Figure 63. SCLOCK Pin I/O Functional Equivalent in I2C Mode

Q2 (OFF)

DVDD

Q4 (OFF)

SDATA/

MOSI

SPE = 1 (SPI ENABLE)

HARDWARE SPI

(MASTER/SLAVE)

Figure 64. SDATA/MOSI Pin I/O Functional Equivalent in SPI Mode

DVDD

MCO

SDATA/

MOSI

(OFF)

50ns GLITCH

REJECTION FILTER

SPE = 0 (I2C ENABLE)

HARDWARE I2C

(SLAVE ONLY)

SFR

BITS

MCI

MDE

I2C M

Figure 65. SDATA/MOSI Pin I/O Functional Equivalent in I2C Mode

Read-Modify-Write Instructions

Some 8051 instructions that read a port read the latch while

others read the pin. The instructions that read the latch rather

than the pins are the ones that read a value, possibly change it,

and then rewrite it to the latch. These are called read-modify-

write instructions, which are listed below. When the destination

operand is a port or a port bit, these instructions read the latch

rather than the pin.

Table 27. Read-Write-Modify Instructions

Instruction

Description

ANL

Logical AND, e.g., ANL P1, A

ORL

(Logical OR, e.g., ORL P2, A

XRL

(Logical EX-OR, e.g., XRL P3, A

JBC

Jump if Bit = 1 and clear bit, e.g., JBC P1.1,

LABEL

CPL

Complement bit, e.g., CPL P3.0

INC

Increment, e.g., INC P2

DEC

Decrement, e.g., DEC P2

DJNZ

Decrement and Jump if Not Zero, e.g., DJNZ

P3, LABEL

MOV PX.Y, C1

Move Carry to Bit Y of Port X

CLR PX.Y1

Clear Bit Y of Port X

SETB PX.Y1

Set Bit Y of Port X

1 These instructions read the port byte (all 8 bits), modify the addressed bit,

and then write the new byte back to the latch.

Read-modify-write instructions are directed to the latch rather

than to the pin to avoid a possible misinterpretation of the

voltage level of a pin. For example, a port pin might be used to

drive the base of a transistor. When 1 is written to the bit, the

transistor is turned on. If the CPU then reads the same port bit

at the pin rather than the latch, it reads the base voltage of the

transistor and interprets it as a Logic 0. Reading the latch rather

than the pin returns the correct value of 1.

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