THS1031CPWR datasheet(31/41 Pages) TI

31 / 41 page

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

driving the internal reference buffer (top/bottom mode)

Figure 36 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal

reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.

AVDD

AGND

AVDD + REFTS + REFBS

REFTS

REFBS

RIN

14 k

Ω

Mode =

AVDD

Figure 36. Equivalent Circuit of Inputs to Internal Reference Buffer

Equations for the currents flowing into REFTS and REFBS are:

REFTS

* AV

DD *

REFBS )

)

REFBS

* AV

DD *

REFTS )

)

These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving

the sample and hold. Tolerance on these currents are

±50%.

driving REFTS and REFBS

7 pF

AVDD

AGND

CLK

0.6 pF

CSAMPLE

VLAST

REFTS

REFBS

Mode = AVDD

Internal

Reference

Buffer

Figure 37. Equivalent Circuit of REFTS and REFBS Inputs

This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also

driving a switched capacitor load like AIN, but with the sampling capacitor and CP2 on each pin now being 0.6 pF

and about 0.6 pF respectively.

(18)

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