THS1031CPWR datasheet(17/41 Pages) TI

17 / 41 page

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

full external reference mode (mode = AGND) (continued)

AIN

REFTS

REFBS

REFTF

REFBF

REFSENSE

MODE

AVDD

+FS

–FS

0.1

µF

0.1

µF

0.1

µF

AVDD

+ [(FS+) – (FS–)]

AVDD

REFT =

GAIN

– [(FS+) – (FS–)]

AVDD

REFB =

GAIN

Figure 14. Full External Reference With Kelvin Connections

differential mode (mode = AVDD/2)

Sample

and

Hold

–1/2

ADC

Core

PGA

REFTF =

REFBF =

AIN+

REFTS

REFBS

Internal

Reference

Buffer

VREF

AGND

AVDD + VREF

AVDD – VREF

AIN–

Figure 15. ADC Reference Generation, MODE = AVDD/2

When MODE = AVDD/2, the internal reference buffer is enabled, its outputs internally switched to REFTF and

REFBF and inputs internally switched to VREF and AGND as shown in Figure 15. The REFTF and REFBF

voltages are centered on AVDD/2 by the internal reference buffer and the voltage difference between REFTF

and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are

open in this mode, allowing REFTS and REFBS to form the AIN– to the sample and hold.

Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to

an internally generated voltage of 1 V, 2 V, or an intermediate voltage (see the onboard reference generator

configuration).

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