THS1031CPWR datasheet(25/41 Pages) TI

25 / 41 page

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

clamp operation (continued)

Line Sync

Black

Level

Video at AIN

CLAMP

Figure 29. Example Waveforms for Line-Clamping to a Video Input Black Level

clamp DAC output voltage range and limits

When using the internal clamp DAC in top/bottom or center span mode, the user must ensure that the desired

dc clamp level at AIN lies within the voltage range VREFBF to VREFTF. This is because the clamp DAC voltage

is constrained to lie within this range VREFBF to VREFTF. Specifically:

VDAC

+ V

REFBF ) (VREFTF * VREFBF)

(0.006

) 0.988

(DAC code) 1024)

DAC codes can range from 0 to 1023. Figure 30 graphically shows the clamp DAC output voltage versus the

DAC code.

VDAC

1023

VREFBF + 0.006(VREFTF–VREFBF)

VREFBF + 0.987(VREFTF–VREFBF)

DAC Code

VREFTF

VREFBF

Figure 30. Clamp DAC Output Voltage Versus DAC Register Code Value

If the desired dc level at AIN does not lie within the voltage range VREFTF to VREFBF, then either the CLAMPIN

pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application

to move the AIN input range into the CLAMP DAC voltage range. This is achieved in both top/bottom and center

span modes by shifting both REFTS and REFBS up or down by the voltage through which the AIN input range

is to be moved.

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THS1031CPWR Datasheet(PDF) 25 Page - Texas Instruments