THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

sample-and-hold

restoration using the THS1031 clamp circuit.

pins, to give a differential output VP+ – VP– = VP given by:

Where:

VM

+

(REFTS

) REFBS)

2

For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However if

pair of differential inputs (see Figures 15 and 16).

programmable gain amplifier

VQ

= Gain

The default PGA gain at power up is 1, but can be programmed from 0.5 to 4.0 via the control register.

analog-to-digital converter

In all operating configurations, VQ is digitized against ADC reference voltages REFTF and REFBF, full-scale

values of VQ being given by

VQFS

)+

) (REFTF * REFBF)

2

VQFS

*+

* (REFTF * REFBF)

2

VQ voltages outside the range VQFS– to VQFS+ lie outside the conversion range of the ADC. Attempts to

convert out-of-range inputs are signalled to the application by driving the OVR output pin high. VQ voltages less

than VQFS – give ADC output code 0. VQ voltages greater than VQFS+ give output code 1023.

complete system

Combining equations 1 to 3, the analog full-scale input voltages at AIN which give VQFS+ and VQFS– at the

PGA output are:

A

IN +

FS

)+ VM )

(REFTF

* REFBF)

(2

Gain)

and

A

IN +

FS

*+ VM *

(REFTF

* REFBF)

(2

Gain)

The analog input span (voltage range) that lies within the ADC conversion range is:

Input span

+ [(FS )) * (FS *)] + (REFTF * REFBF) Gain

(1)

(2)

(3)

(4)

(5)

(6)