THS1031CPWR datasheet(19/41 Pages) TI

19 / 41 page

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

top/bottom mode (MODE = AVDD)

Sample

and

Hold

–1/2

ADC

Core

PGA

REFTF = AVDD + (REFTS – REFBS)

AIN+

REFTS

REFBS

Internal

Reference

Buffer

REFBF = AVDD – (REFTS – REFBS)

Figure 18. ADC Reference Generation Mode = AVDD

Connecting MODE to AVDD enables the internal reference buffer. Its inputs are internally switched to the REFTS

and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections

(REFTS to REFTF) and (REFBS to REFBF) are broken.

To match the signal span to the full ADC input span, the voltage difference between REFTS and REFBS should

be REFTS – REFBS = [(FS+) – (FS–)]

× Gain, with the average of the REFTS and REFBS voltages being the

AIN midscale voltage, VM.

Typically, REFSENSE is tied to AVDD to disable the ORG output to VREF (as in Figure 19), but the user can

choose to use the ORG output to VREF as either REFTS or REFBS.

AIN

REFTS

REFBS

REFTF

REFBF

REFSENSE

MODE

AVDD

+FS

–FS

DC SOURCE = VM + [(FS+) – (FS–)]

DC SOURCE =VM – [(FS+) – (FS–)]

0.1

µF

0.1

µF

0.1

µF

GAIN

Figure 19. ADC Reference Generation Mode = AVDD

THS1031CPWR Datasheet(PDF) 19 Page - Texas Instruments

THS1031CPWR Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL