THS1031CPWR datasheet(33/41 Pages) TI

33 / 41 page

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

clamp acquisition time (continued)

For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of

1.3 V at the THS1031 input. The voltage Vc required across the input coupling capacitor is thus 1.3 – 0.3 = 1 V.

If a 10 mV or less clamp voltage error Ve will give acceptable system operation, if the source resistance Rin is

Ω and the coupling capacitor CIN is 1 µF, then the total clamp pulse duration required to reach this error is:

ACQ +

+ 1 mF

0.01

= 92

µs (approximately)

Note that SW1 does not have to be closed continuously until the desired clamp voltage is achieved. The clamp

level can be acquired over a longer interval by using a series of shorter clamp pulses with total pulse duration

at least equal to the acquisition time calculated using equation 19.

droop

The charge pulses entering or leaving AIN caused by the sample and hold switched capacitor input can charge

or discharge CIN, causing the voltage at AIN to drift toward VM (the average of REFTS and REFBS) during the

time between clamp pulses. This effect is called clamp droop and can be seen as a slow change in the ADC

output code when the input signal is a constant dc level. Through careful clamp circuit design, this droop can

be kept below 1 LSB, giving no change in the ADC output between clamp pulses.

The clamp voltage droop is a function of the input current to the THS1031 and the time between clamp pulses,

DROOP +

td (approximately)

Where:

IN +

AIN

– VM)

AIN

+ (V

AIN – VM)

fclk

RAIN is the input resistance given by equation 20. Cs is approximately 2.5 pF. Substituting IIN into the droop

voltage equation gives

DROOP +

AIN – VM)

IN)

Note that IIN has maximum value when VAIN is either +FS or –FS, and so the droop rate is worst then the clamp

level is near either full-scale input voltage. There is no droop when the clamp level equals VM because IIN is

zero. Note that the actual voltage droop may be up to 50% more than given by equation 22 when allowing for

temperature variations and device to device processing variations.

For example, with CIN = 1 µF at fclk = 30 MSPS conversion rate in top/bottom mode with REFTS = 2.5 V and

REFBS = 0.5 V, the clamp droop over td = 63.5 ms when VAIN = +FS is

DROOP +

AIN – VM)

fclk

IN)

+ (2.5 V – 1.5 V)

2.5 pF

30 MMz

+ 0.0024 mV

+ 1.25 LSB (assuming PGA gain + 1)

(20)

(21)

(22)

(23)

THS1031CPWR Datasheet(PDF) 33 Page - Texas Instruments

THS1031CPWR Datasheet(HTML) 33 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL