THS1031CPWR datasheet(22/41 Pages) TI

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THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

onboard reference generator configuration (continued)

VBG

Internal

Reference

Buffer

Mode =

REFSENSE

AGND

VREF = External

AVDD

Figure 23. Drive VREF Mode

operating configuration examples

This section provides examples of operating configurations.

Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF

to drive REFTS and with PGA gain = 1. Connecting the MODE pin to AVDD puts the THS1031 in top/bottom

mode. Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are

user-connected to VREF and AGND respectively to match the AIN pin input range to the voltage range of the

input signal.

AIN

REFTF

REFBF

REFSENSE

MODE

AVDD

2 V

0 V

0.1

µF

0.1

µF

0.1

µF

1 V

VREF = 2 V

REFTS

REFBS

Figure 24. Operation Configuration in Top/Bottom Mode

THS1031CPWR Datasheet(PDF) 22 Page - Texas Instruments

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