THS1031CPWR datasheet(15/41 Pages) TI

15 / 41 page

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

complete system (continued)

The REFTF and REFBF voltage difference and the gain sets the device input range. The next sections describe

in detail the various methods available for setting voltages REFTF and REFBF to obtain the desired input span

and device performance.

ADC reference generation

The THS1031 has three primary modes of ADC reference generation, selected by the voltage level applied to

the MODE pin.

Connecting the MODE pin to AGND gives full external reference mode. In this mode, the user supplies the ADC

reference voltages directly to pins REFTF and REFBF. This mode is used where there is need for minimum

power drain or where there are very tight tolerances on the ADC reference voltages. This mode also offers the

possibility of Kelvin connection of the reference inputs to the THS1031 to eliminate any voltage drops from

remote references that may occur in the system. Only single-ended input is possible in this mode.

Connecting the MODE pin to AVDD/2 gives differential mode. In this mode, the ADC reference voltages REFTF

and REFBF are generated by the internal reference buffer from the voltage applied to the VREF pin. This mode

is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins.

A special case of differential mode is center span mode, in which user applies a single-ended signal to AIN and

applies the mid-scale input voltage (VM) to the REFTS and REFBS pins.

Connecting the MODE pin to AVDD gives top/bottom mode. In this mode, the ADC reference voltages REFTF

and REFBF are generated by the internal reference buffer from the voltages applied to the REFTS and REFBS

pins. Only single-ended input is possible in top/bottom mode.

Table 1. Typical Set of Reference Connections

REFERENCE MODE

MODE

REFSENSE

VREF

VOLTAGE

REFTS, REFBS

ANALOG INPUT

FIGURES

External

AVSS

AVDD

Disabled

Reference buffer powered

down, reference voltage pro-

vided directly by REFTS and

REFBS

Single-ended

12, 13, 14

VREF

1 V

E t

t REFTS

Internal

AVDD/2

AGND

2 V

Externally connect REFTS

to REFBS This pair then

Differential or

15 16 17

Internal

AVDD/2

External

divider

1 + Ra/Rb

(see Figure 22)

to REFBS. This air then

forms AIN– to the ADC.

center span

15, 16, 17

External (through internal

reference buffer)

AVDD

Disabled

REFTS = VMID + (VFS+ –

Single-ended

Output of VREF can be

AVDD

VREF

1 V

VFS–) × Gain/2

18 19

Out ut of VREF can be

externally tied to REFTS or

AVDD

AGND

2 V

REFBS = VMID – (VFS+ –

(top-bottom

18, 19

REFBS to provide one of the

reference voltages

External

divider

1 + Ra/Rb

(see Figure 22)

REFBS

VMID (VFS+

VFS–) × Gain/2

(to bottom

mode)

THS1031CPWR Datasheet(PDF) 15 Page - Texas Instruments

THS1031CPWR Datasheet(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL