THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

34

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

clamp operation (continued)

Thus if a constant voltage is applied to the clamp input that drives the ADC output to code 1023 (with no

over-range), then the ADC output code will slowly drop to code 1022, or possibly code 1021, over the period

and hence reduce the voltage change between clamp pulses.

If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly

larger than calculated above due to the capacitor’s rapid rate of self-discharge. Avoid using electrolytic and

tantalum coupling capacitors as these usually exhibit much higher leakage then nonpolarized capacitor types.

Electrolytic and tantalum capacitors also tend to have higher parasitics inductance, which can cause further

problems at high input frequencies.

steady-state clamp voltage error

Under steady-state conditions, the change in the clamp voltage caused during clamping must equal the change

caused by clamp droop, otherwise the effect causing the largest voltage change would pull the clamp voltage

away until these charging and droop effects equalize.

V

COS

VDROOP = ∆VAIN

tc

td

V(Clamp)

VAIN

VM

Figure 40. Approximate Waveforms at AIN During Droop and Clamping

The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming

is then

DV

AIN +

V

COS

R

IN

tc

The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the

droop voltage to the clamp acquisition voltage change gives

V

COS +

R

IN

I

IN

td

tc

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