THS1031CPWR datasheet(27/41 Pages) TI

27 / 41 page

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

digital control registers

The THS1031 contains two clamp registers and a control register for user programming of THS1031 operation.

Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE pins (see the

previous section). In input mode, the two I/O bus MSBs are address bits, 00 addressing clamp register 1, 01

clamp register 2, and 10 the control register.

Table 3. Register Map

ADDRESS

DESCRIPTION

DEF

BIT

I/O[9:8]

DESCRIPTION

(HEX)

Clamp Reg. 1

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

Clamp Reg. 2

DAC[9]

DAC[8]

Control Reg.

CLDIS

TWOC

CLINT

PDWN

PGA[2]

PGA[1]

PGA[0]

Reserved

Table 4. Register Contents

BIT NO

BIT NAME(S)

DEFAULT

DESCRIPTION

2:0

PGA[2:0]

PGA gain:

000 = 0.5

001 = 1.0 (default value)

010 = 1.5

011 = 2.0

100 = 2.5

101 = 3.0

110 = 3.5

111 = 4.0

Control Register

I/O[9:8] = 10

PDWN

Power down

0 = THS1031 powered up

1 = THS1031 powered down

I/O[9:8] = 10

CLINT

Clamp voltage internal/external

0 = external analog clamp voltage from CLAMPIN pin

1 = from onboard DAC (see clamp register)

TWOC

Output format

0 = unsigned binary

1 = two’s complement

CLDIS

Clamp amplifier disable (for power saving)

0 = Enable

1 = Disable

Unused

Clamp Register 1

I/O[9:8] = 00

7:0

DAC[7:0]

Clamp DAC voltage

(DAC[0] = LSB.)

DAC[9:0] = 00h: Clamp voltage = REFBF

DAC[9:0] = 3Fh: Clamp voltage = REFTF

Clamp Register 2

7:2

Unused

Clamp Register 2

I/O[9:8] = 01

1:0

DAC[9:8]

Clamp DAC voltage

(DAC[9] = MSB)

THS1031CPWR Datasheet(PDF) 27 Page - Texas Instruments

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