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TAS5760LD Datasheet(PDF) 41 Page - Texas Instruments |
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TAS5760LD Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 54 page ![]() 1.0 UF 0.22UF 0.22UF 0.22UF 0.22UF 1 UF RUVP1 RUVP2 1.5UF 10 l3 5.6 l3 10 l3 220 pF HP LD 1.5UF 10 l3 5.6 l3 10 l3 220 pF 1 UF 1 UF Gain Set by Pin Decode 1.0 UF RCLIP2 System Processor & Associated Passive Components 1.0 UF RCLIP1 LFILT LFILT CFILT CFILT LFILT LFILT CFILT CFILT 1.0 UF 1.0 UF HIGH Æ fSPK_AMP = 8 * fS LOW Æ fSPK_AMP = 16 * fS 10 l3 VDD VDD 38 39 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 37 36 35 34 33 32 31 30 29 28 27 26 25 10 11 ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN1 SPK_SLEEP/ADR MCLK SDIN LRCK DGND DR_INA- DR_INA+ DR_OUTA DRGND DR_MUTE DR_CN DRVSS SCLK SPK_GAIN0 SFT_CLIP GGND AVDD PVDD PVDD BSTRPA+ SPK_OUTA+ PGND SPK_OUTA- BSTRPB+ SPK_OUTB- PGND BSTRPB- PVDD PVDD DR_INB- DR_INB+ DR_OUTB DR_UVE DRGND DR_CP DRVDD SPK_OUTB+ BSTRPA- GVDD_REG PVDD 0.1 UF 0.1 UF 470 UF VDD TAS5760LD www.ti.com SLOS781 – JULY 2013 Figure 45. Stereo BTL using Hardware Control Copyright © 2013, Texas Instruments Incorporated 41 Product Folder Links: TAS5760LD |
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