TAS5760LD datasheet(23/54 Pages) TI

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TAS5760LD

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SLOS781 – JULY 2013

Figure 39. Digital Clipper Example Waveform for various settings of Digital Clip Level [19:0]

It is important to note that the actual signal developed across the speaker will be determined not only by the

digital clipper, but also the analog gain of the amplifier. Depending on the analog gain settings and the PVDD

level applied, clipping could occur as a result of the voltage swing that is determined by the gain being larger

than the available PVDD supply rail. The gain structures are discussed in detail below for both Hardware Control

Mode and Software Control Mode.

Closed Loop Class-D Amplifier

Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose

first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two

pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker

amplifer. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and

increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D

amplifier section of the device. The gain structures are discussed in detail below for both Hardware Control Mode

and Software Control Mode.

The switching rate of the amplifier is configurable in both Hardware Control Mode and Software Control Mode. In

both cases, the PWM switching frequency is a multiple of the sample rate. This behavior is described in the the

respective Hardware Control Mode and Software Control Mode sections below.

Speaker Amplifier Protection Suite

The speaker amplifier in the TAS5760LD includes a robust suite of error handling and protection features. It is

protected against Over-Current, Under-Voltage, Over-Voltage, Over-Temperature, DC, and Clock Errors. The

status of these errors is reported via the SPK_FAULT pin and the appropriate error status register in the I²C

Control Port. The error or handling behavior of the device is characterized as being either "Latching" or "Non-

Latching" depending on what is required to clear the fault and resume normal operation (that is playback of

audio).

For latching errors, the SPK_SD pin or the SPK_SD bit in the control port must be toggled in order to clear the

error and resume normal operation. If the error is still present when the SPK_SD pin or bit transitions from

"LOW" back to "HIGH", the device will again detect the error and enter into a fault state resulting in the error

status bit being set in the control port and the SPK_FAULT line being pulled "LOW". If the error has been cleared

(for example, the temperature of the device has decreased below the error threshold) the device will attempt to

resume normal operation after the SPK_SD pin or bit is toggled and the required fault time out period

(TSPK_FAULT ) has passed. If the error is still present, the device will once again enter a fault state and must be

placed into and brought back out of shutdown in order to attempt to clear the error.

For non-latching errors, the device will automatically resume normal operation (that is playback) once the error

has been cleared. The non-latching errors, with the exception of clock errors will not cause the SPK_FAULT line

to be pulled "LOW". It is not necessary to toggle the SPK_SD pin or bit in order to clear the error and resume

normal operation for non-latching errors. Table 1 details the types of errors protected by the TAS5760LD's

Protection Suite and how each are handled.

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TAS5760LD Datasheet(PDF) 23 Page - Texas Instruments