TAS5760LD datasheet(21/54 Pages) TI

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Digital to PWM

Conversion

Digital

Boost

Volume

Control

Full Bridge

Power Stage

Serial

Audio

Port

Full Bridge

Power Stage

Gate

Drives

Gate

Drives

Digital

Clipper

Closed Loop Class D Amplifier

Digital Gain

(GDIG)

Analog Gain

(GANA)

011010..

Serial

Audio In

PWM

Audio Out

HPF

Interpolation

Filter

SFT_CLIP

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TAS5760LD

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SLOS781 – JULY 2013

Speaker Amplifier Audio Signal Path

The block diagram for the TAS5760LD's speaker amplifier is shown below. In Hardware Control mode, a limited

subset of audio path controls are made available via external pins, which are pulled "HIGH" or "LOW" to

configure the device. In Software Control Mode, the additional features and configurations are available. All of

the available controls are discussed in this section, and the subset of controls that available in Hardware Control

Mode are discussed in its respective section below.

Serial Audio Port (SAP)

The serial audio port (SAP) receives audio in either I²S, Left Justified, or Right Justified formats. In Hardware

Control mode, the device operates only in 32, 48 or 64 x fS I²S mode. In Software Control mode, additional

options for left-justified and right justified audio formats are available. The supported clock rates and ratios for

Hardware Control Mode and Software Control Mode are detailed in their respective sections below.

I²S Timing

I²S timing uses LRCK to define when the data being transmitted is for the left channel and when it is for the right

channel. LRCK is "LOW" for the left channel and "HIGH" for the right channel. A bit clock, called SCLK, runs at

32, 48, or 64 × fS and is used to clock in the data. There is a delay of one bit clock from the time the LRCK signal

changes state to the first bit of data on the data lines. The data is presented in 2's-complement form (MSB-first)

and is valid on the rising edge of bit clock.

Left-Justified

Left-justified (LJ) timing also uses LRCK to define when the data being transmitted is for the left channel and

when it is for the right channel. LRCK is "HIGH" for the left channel and "LOW" for the right channel. A bit clock

running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the

same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The

TAS5760LD can accept digital words from 16 to 24 bits wide and pads any unused trailing data-bit positions in

the L/R frame with zeros before presenting the digital word to the audio signal path.

Right-Justified

Right-justified (RJ) timing also uses LRCK to define when the data being transmitted is for the left channel and

when it is for the right channel. LRCK is "HIGH" for the left channel and "LOW" for the right channel. A bit clock

running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock

periods (for 24-bit data) after LRCK toggles. In RJ mode the LSB of data is always clocked by the last bit clock

before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The

TAS5760LD pads unused leading data-bit positions in the left/right frame with zeros before presenting the digital

word to the audio signal path.

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