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AFE4490 Datasheet(PDF) 9 Page - Texas Instruments |
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AFE4490 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 69 page  A7 A6 A1 A0 SPI STE SPI SIMO SCLK tSTECLK tSIMOSU tSIMOHD 31 0 D23 D22 D1 D0 23 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 PARAMETRIC MEASUREMENT INFORMATION (continued) Figure 2. Serial Interface Timing Diagram, Write Operation Table 1. Timing Requirements for Figure 1 and Figure 2 PARAMETER MIN TYP MAX UNIT tCLK Clock frequency on XIN pin 8 MHz tSCLK Serial shift clock period 62.5 ns tSTECLK STE low to SCLK rising edge, setup time 10 ns tCLKSTEH,L SCLK transition to SPI STE high or low 10 ns tSIMOSU SIMO data to SCLK rising edge, setup time 10 ns tSIMOHD Valid SIMO data after SCLK rising edge, hold time 10 ns tSOMIPD SCLK falling edge to valid SOMI, setup time 17 ns tSOMIHD SCLK rising edge to invalid data, hold time 0.5 tSCLK Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: AFE4400 |
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