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EP3SL70 Datasheet(PDF) 187 Page - Altera Corporation

Part # EP3SL70
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SL70 Datasheet(HTML) 187 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–177
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–92 lists the EP3SL340 row pins input timing parameters for single-ended I/O
standards.
3.0-V
PCI-X
GCLK
t
su
-1.356
-1.346
-2.016 -2.063 -2.329 -2.244 -2.541 -2.063 -2.329 -2.244 -2.541
ns
t
h
1.497
1.487
2.231
2.286
2.573
2.475
2.782
2.286
2.573
2.475
2.782
ns
GCLK
PLL
t
su
-1.702
-1.702
-2.553 -2.587 -2.889 -2.798 -3.372 -2.587 -2.889 -2.798 -3.372
ns
t
h
2.007
2.007
3.030
3.083
3.433
3.312
3.911
3.083
3.433
3.312
3.911
ns
Table 1–91. EP3SL340 Column Pins Input Timing Parameters (Part 4 of 4)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
Table 1–92. EP3SL340 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-1.239
-1.296
-1.925
-1.956 -2.199 -2.135 -2.587 -1.973 -2.204 -2.142 -2.522
ns
t
h
1.362
1.435
2.137
2.177
2.442
2.366
2.822
2.205
2.456
2.382
2.763
ns
GCLK
PLL
t
su
0.879
0.945
1.670
1.687
1.786
1.680
1.689
1.689
1.807
1.695
1.746
ns
t
h
-0.615
-0.660
-1.216
-1.217 -1.263 -1.188 -1.178 -1.208 -1.273 -1.193 -1.231
ns
3.3-V
LVCMOS
GCLK
t
su
-1.239
-1.296
-1.925
-1.956 -2.199 -2.135 -2.587 -1.973 -2.204 -2.142 -2.522
ns
t
h
1.362
1.435
2.137
2.177
2.442
2.366
2.822
2.205
2.456
2.382
2.763
ns
GCLK
PLL
t
su
0.879
0.945
1.670
1.687
1.786
1.680
1.689
1.689
1.807
1.695
1.746
ns
t
h
-0.615
-0.660
-1.216
-1.217 -1.263 -1.188 -1.178 -1.208 -1.273 -1.193 -1.231
ns
3.0-V LVTTL
GCLK
t
su
-1.245
-1.307
-1.922
-1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
ns
t
h
1.368
1.446
2.134
2.178
2.445
2.369
2.825
2.204
2.461
2.387
2.768
ns
GCLK
PLL
t
su
0.873
0.934
1.673
1.686
1.783
1.677
1.686
1.690
1.802
1.690
1.741
ns
t
h
-0.609
-0.649
-1.219
-1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
ns
3.0-V
LVCMOS
GCLK
t
su
-1.245
-1.307
-1.922
-1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
ns
t
h
1.368
1.446
2.134
2.178
2.445
2.369
2.825
2.204
2.461
2.387
2.768
ns
GCLK
PLL
t
su
0.873
0.934
1.673
1.686
1.783
1.677
1.686
1.690
1.802
1.690
1.741
ns
t
h
-0.609
-0.649
-1.219
-1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
ns
2.5 V
GCLK
t
su
-1.233
-1.300
-1.931
-1.970 -2.217 -2.153 -2.605 -1.981 -2.219 -2.157 -2.537
ns
t
h
1.356
1.439
2.143
2.191
2.460
2.384
2.840
2.213
2.471
2.397
2.778
ns
GCLK
PLL
t
su
0.885
0.941
1.664
1.673
1.768
1.662
1.671
1.681
1.792
1.680
1.731
ns
t
h
-0.621
-0.656
-1.210
-1.203 -1.245 -1.170 -1.160 -1.200 -1.258 -1.178 -1.216
ns
1.8 V
GCLK
t
su
-1.251
-1.343
-1.980
-1.995 -2.204 -2.138 -2.582 -2.003 -2.208 -2.153 -2.621
ns
t
h
1.377
1.482
2.193
2.216
2.447
2.369
2.817
2.234
2.461
2.393
2.859
ns
GCLK
PLL
t
su
0.827
0.910
1.624
1.634
1.857
1.742
1.565
1.620
1.886
1.762
1.619
ns
t
h
-0.562
-0.624
-1.170
-1.164 -1.330 -1.246 -1.060 -1.140 -1.347 -1.255 -1.107
ns



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