EP3SL70 datasheet(191/341 Pages) ALTERA

191 / 341 page

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

1–181

I/O Timing

Altera Corporation

Stratix III Device Handbook, Volume 2

3.0-V

LVCMOS

4mA

GCLK

tco

3.583

5.243

5.427

5.947

5.800

6.228

5.427 5.947 5.800 6.228

GCLK

PLL

4.149

6.087

6.279

6.903

6.724

7.265

6.279 6.903 6.724 7.265

8mA

GCLK

tco

3.504

5.120

5.298

5.812

5.665

6.093

5.298 5.812 5.665 6.093

GCLK

PLL

4.070

5.963

6.149

6.793

6.614

7.155

6.149 6.793 6.614 7.155

12mA

GCLK

3.499

5.112

5.291

5.804

5.656

6.085

5.291 5.804 5.656 6.085

GCLK

PLL

4.063

5.955

6.142

6.761

6.581

7.124

6.142 6.761 6.581 7.124

16mA

GCLK

3.490

5.098

5.276

5.789

5.641

6.070

5.276 5.789 5.641 6.070

GCLK

PLL

4.054

5.940

6.126

6.767

6.588

7.129

6.126 6.767 6.588 7.129

2.5 V

4mA

GCLK

3.705

5.450

5.654

6.194

6.047

6.475

5.654 6.194 6.047 6.475

GCLK

PLL

4.269

6.293

6.504

7.111

6.932

7.473

6.504 7.111 6.932 7.473

8mA

GCLK

3.605

5.331

5.528

6.062

5.915

6.343

5.528 6.062 5.915 6.343

GCLK

PLL

tco

4.172

6.174

6.379

6.987

6.808

7.349

6.379 6.987 6.808 7.349

12mA

GCLK

3.561

5.244

5.438

5.967

5.819

6.248

5.438 5.967 5.819 6.248

GCLK

PLL

tco

4.127

6.087

6.288

6.909

6.730

7.271

6.288 6.909 6.730 7.271

16mA

GCLK

3.523

5.205

5.395

5.924

5.776

6.205

5.395 5.924 5.776 6.205

GCLK

PLL

4.088

6.048

6.246

6.852

6.673

7.214

6.246 6.852 6.673 7.214

Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part 2 of 7)

I/O

Standard

Clock

Fast Model

C4L

I4L

Units

Industrial

Commercial

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

0.9 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

0.9 V

EP3SL70 Datasheet(PDF) 191 Page - Altera Corporation

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