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EP3SL70 Datasheet(PDF) 217 Page - Altera Corporation

Part # EP3SL70
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SL70 Datasheet(HTML) 217 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–207
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
1.5-V HSTL
CLASS I
GCLK
t
su
1.009
1.009
-1.308 -1.462 -1.641 -1.555 -1.578 -1.452
-1.632
-1.544
-1.622
ns
t
h
0.867
0.912
1.600
-1.210 -1.310 -1.259 -1.534 -1.219
-1.316
-1.267
-1.571
ns
GCLK
PLL
t
su
-0.902
-0.937
1.491
1.416
1.541
1.476
1.748
1.435
1.557
1.494
1.786
ns
t
h
1.015
1.063
-1.308
1.910
2.142
2.025
2.053
1.908
2.141
2.023
2.100
ns
1.5-V HSTL
CLASS II
GCLK
t
su
0.946
0.949
1.600
-1.462 -1.641 -1.555 -1.578 -1.452
-1.632
-1.544
-1.622
ns
t
h
-0.697
-0.689
1.491
-1.210 -1.310 -1.259 -1.534 -1.219
-1.316
-1.267
-1.571
ns
GCLK
PLL
t
su
-0.902
-0.937
1.491
1.416
1.541
1.476
1.748
1.435
1.557
1.494
1.786
ns
t
h
1.015
1.063
1.491
1.910
2.142
2.025
2.053
1.908
2.141
2.023
2.100
ns
1.2-V HSTL
CLASS I
GCLK
t
su
0.946
0.949
1.491
-1.462 -1.641 -1.555 -1.578 -1.452
-1.632
-1.544
-1.622
ns
t
h
-0.697
-0.689
1.491
-1.210 -1.310 -1.259 -1.534 -1.219
-1.316
-1.267
-1.571
ns
GCLK
PLL
t
su
-0.896
-0.926
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451
-1.663
-1.612
-1.927
ns
t
h
1.009
1.052
1.597
1.816
1.931
1.813
1.843
1.809
1.936
1.818
1.895
ns
1.2-V HSTL
CLASS II
GCLK
t
su
0.952
0.960
1.494
1.640
1.888
1.819
2.111
1.667
1.903
1.836
2.144
ns
t
h
-0.703
-0.700
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451
-1.663
-1.612
-1.927
ns
GCLK
PLL
t
su
-0.896
-0.926
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451
-1.663
-1.612
-1.927
ns
t
h
1.009
1.052
1.597
1.816
1.931
1.813
1.843
1.809
1.936
1.818
1.895
ns
3.0-V PCI
GCLK
t
su
0.952
0.960
1.494
1.640
1.888
1.819
2.111
1.667
1.903
1.836
2.144
ns
t
h
-0.703
-0.700
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450
-1.668
-1.617
-1.932
ns
GCLK
PLL
t
su
-0.902
-0.937
1.491
1.641
1.891
1.822
2.114
1.666
1.908
1.841
2.149
ns
t
h
1.015
1.063
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450
-1.668
-1.617
-1.932
ns
3.0-V
PCI-X
GCLK
t
su
0.946
0.949
1.600
1.815
1.928
1.810
1.840
1.810
1.931
1.813
1.890
ns
t
h
-0.697
-0.689
1.491
1.641
1.891
1.822
2.114
1.666
1.908
1.841
2.149
ns
GCLK
PLL
t
su
-0.902
-0.937
1.500
1.654
1.906
1.837
2.129
1.675
1.918
1.851
2.159
ns
t
h
1.015
1.063
-1.317 -1.447 -1.676 -1.623 -1.914 -1.459
-1.678
-1.627
-1.942
ns
Table 1–102. EP3SE50 Row Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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