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EP3SL340 Datasheet(PDF) 75 Page - Altera Corporation |
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EP3SL340 Datasheet(HTML) 75 Page - Altera Corporation |
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75 / 341 page ![]() Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–65 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Table 1–49 and Table 1–50 list the EP3SL50 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1–49 lists the EP3SL50 column pin delay adders when using the regional clock. Table 1–50 lists the EP3SL50 row pin delay adders when using the regional clock. DIFFERENTIAL 2.5-V SSTL CLASS II 16mA GCLK tco 3.076 3.311 4.709 5.123 5.649 5.505 5.704 5.258 5.787 5.643 5.772 ns GCLK PLL t co 3.062 3.295 4.686 5.099 5.624 5.480 5.679 5.234 5.762 5.618 5.747 ns Table 1–48. EP3SL50 Row Pins Output Timing Parameters (Part 4 of 4) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–49. EP3SL50 Column Pin Delay Adders for Regional Clock Parameter Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V RCLK input adder 0.239 0.258 0.341 0.365 0.39 0.377 0.439 0.375 0.399 0.388 0.441 ns RCLK PLL input adder 0.008 0.009 0.014 0.017 0.019 0.017 0.02 0.018 0.019 0.017 0.02 ns RCLK output adder -0.068 -0.07 -0.09 -0.092 -0.094 -0.091 -0.169 -0.086 -0.087 -0.09 -0.17 ns RCLK PLL output adder 1.614 1.649 2.575 2.89 3.164 3.011 3.22 2.908 3.217 3.063 3.338 ns Table 1–50. EP3SL50 Row Pin Delay Adders for Regional Clock Parameter Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V RCLK input adder 0.111 0.124 0.178 0.193 0.208 0.2 0.263 0.197 0.213 0.203 0.266 ns RCLK PLL input adder 0.101 0.107 0.156 0.174 0.194 0.184 0.251 0.177 0.196 0.188 0.249 ns RCLK output adder -0.113 -0.127 -0.181 -0.196 -0.213 -0.205 -0.271 -0.199 -0.217 -0.209 -0.273 ns RCLK PLL output adder -0.107 -0.113 -0.164 -0.185 -0.213 -0.2 -0.266 -0.184 -0.212 -0.198 -0.262 ns |
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