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EP3SL340 Datasheet(PDF) 24 Page - Altera Corporation |
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EP3SL340 Datasheet(HTML) 24 Page - Altera Corporation |
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24 / 341 page  Table 1–20. PLL Specifications for Stratix III Devices (Part 1 of 3) Symbol Parameter C2 C3, I3 C4, I4 C4L, I4L Unit V CCL = 1.1 V V CCL = 1.1 V V CCL = 1.1 V V CCL = 1.1 V V CCL = 0.9 V Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max f IN Input clock frequency 5 — 800 (1) 5— 717 (1) 5— 717 (1) 5— 717 (1) 5— 717 (1) MHz f INPFD Input frequency to the PFD 5 — 325 5 — 325 5 — 325 5 — 325 5 — 325 MHz f VCO PLL VCO operating range 600 — 1600 600 — 1300 600 — 1300 600 — 1300 600 — 1300 MHz t EINDUTY Input clock or external feedback clock input duty cycle 40 — 60 40 — 60 40 — 60 40 — 60 40 — 60 % f OUT Output frequency for internal global or regional clock —— 600 (2) —— 500 (2) —— 450 (2) —— 450 (2) —— 375 (2) MHz f OUT_EXT Output frequency for dedicated external clock output —— 800 (2) —— 717 (2) —— 717 (2) —— 717 (2) —— 717 (2) MHz t OUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 45 50 55 45 50 55 45 50 55 45 50 55 % t FCOMP External feedback clock compensation time —— 10 —— 10 — — 10 — —10 — —10 ns t CONFIGPLL Time required to reconfigure scan chain — 3.5 — — 3.5 — — 3.5 — — 3.5 — — 3.5 — scanclk cycles t CONFIGPHASE Time required to reconfigure phase shift —1 — — 1 — — 1 — — 1 — —1 — scanclk cycles f SCANCLK scanclk frequency — — 100 — — 100 — — 100 — — 100 — — 100 MHz t LOCK Time required to lock from end of device configuration — — 1— — 1 — — 1— — 1 — — 1 ms t DLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — 1— — 1 — — 1— — 1 — — 1 ms |
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