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EP3SL340 Datasheet(PDF) 277 Page - Altera Corporation |
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EP3SL340 Datasheet(HTML) 277 Page - Altera Corporation |
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277 / 341 page  Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–267 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Table 1–124 lists the EP3SE110 row pins output timing parameters for single-ended I/O standards. 1.2-V HSTL CLASS I 4mA GCLK t co 3.336 3.336 4.703 5.096 5.577 5.442 5.754 5.096 5.577 5.442 5.754 ns GCLK PLL t co 3.716 3.728 5.289 5.719 6.333 6.169 6.571 5.719 6.333 6.169 6.571 ns 6mA GCLK t co 3.328 3.328 4.694 5.087 5.568 5.433 5.745 5.087 5.568 5.433 5.745 ns GCLK PLL t co 3.707 3.720 5.280 5.710 6.324 6.160 6.562 5.710 6.324 6.160 6.562 ns 8mA GCLK t co 3.329 3.329 4.702 5.095 5.577 5.442 5.754 5.095 5.577 5.442 5.754 ns GCLK PLL t co 3.707 3.721 5.287 5.718 6.333 6.169 6.571 5.718 6.333 6.169 6.571 ns 10mA GCLK t co 3.318 3.318 4.689 5.082 5.563 5.428 5.740 5.082 5.563 5.428 5.740 ns GCLK PLL t co 3.697 3.710 5.274 5.704 6.319 6.155 6.557 5.704 6.319 6.155 6.557 ns 12mA GCLK t co 3.318 3.318 4.689 5.082 5.564 5.429 5.741 5.082 5.564 5.429 5.741 ns GCLK PLL t co 3.697 3.710 5.274 5.705 6.320 6.156 6.558 5.705 6.320 6.156 6.558 ns 1.2-V HSTL CLASS II 16mA GCLK t co 3.339 3.339 4.705 5.097 5.577 5.442 5.754 5.097 5.577 5.442 5.754 ns GCLK PLL t co 3.718 3.731 5.290 5.720 6.333 6.169 6.571 5.720 6.333 6.169 6.571 ns 3.0-V PCI — GCLK t co 3.442 3.442 4.750 5.131 5.602 5.467 5.779 5.131 5.602 5.467 5.779 ns GCLK PLL t co 3.821 3.834 5.335 5.756 6.358 6.194 6.596 5.756 6.358 6.194 6.596 ns 3.0-V PCI-X — GCLK t co 3.442 3.442 4.750 5.131 5.602 5.467 5.779 5.131 5.602 5.467 5.779 ns GCLK PLL t co 3.821 3.834 5.335 5.756 6.358 6.194 6.596 5.756 6.358 6.194 6.596 ns Table 1–123. EP3SE110 Column Pins Output Timing Parameters (Part 7 of 7) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L UnitS Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–124. EP3SE110 Row Pins Output Timing Parameters (Part 1 of 5) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V 3.3-V LVTTL 4mA GCLK t co 3.208 3.456 4.797 5.180 5.703 5.543 5.850 5.304 5.827 5.696 5.930 ns GCLK PLL t co 1.452 1.625 2.008 2.086 2.326 2.346 2.347 2.239 2.435 2.455 2.342 ns 8mA GCLK t co 3.142 3.385 4.687 5.069 5.589 5.429 5.736 5.191 5.712 5.581 5.815 ns GCLK PLL t co 1.359 1.554 1.898 1.975 2.181 2.201 2.202 2.098 2.286 2.306 2.193 ns 12mA GCLK t co 3.063 3.296 4.581 4.969 5.493 5.333 5.640 5.092 5.612 5.481 5.715 ns GCLK PLL t co 1.260 1.465 1.792 1.875 2.053 2.073 2.074 1.971 2.154 2.174 2.061 ns |
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