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EP3SL340 Datasheet(PDF) 285 Page - Altera Corporation |
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EP3SL340 Datasheet(HTML) 285 Page - Altera Corporation |
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285 / 341 page  Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–275 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Table 1–127 lists the EP3SE110 column pins output timing parameters for differential I/O standards. DIFFERENTIAL 2.5-V SSTL CLASS II GCLK tsu -0.781 -0.827 -1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712 ns t h 0.907 0.969 1.379 1.502 1.631 1.568 1.912 1.509 1.636 1.573 1.952 ns GCLK PLL t su 1.124 1.141 1.827 2.068 2.299 2.178 2.118 2.089 2.323 2.199 2.170 ns t h -0.861 -0.861 -1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665 ns Table 1–126. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 3) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–127. EP3SE110 Column Pins Output Timing Parameters (Part 1 of 4) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1V V CCL= 1.1V V CCL= 1.1V V CCL= 1.1V V CCL= 0.9V V CCL= 1.1V V CCL= 1.1V V CCL= 1.1V V CCL= 0.9V LVDS_E_1R — GCLK tco 3.152 3.387 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 ns GCLK PLL t co 1.328 1.502 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns LVDS_E_3R — GCLK t co 3.148 3.390 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 ns GCLK PLL t co 1.324 1.505 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns MINI- LVDS_E_1R — GCLK t co 3.152 3.387 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 ns GCLK PLL t co 1.328 1.502 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns MINI- LVDS_E_3R — GCLK t co 3.148 3.390 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 ns GCLK PLL t co 1.324 1.505 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns RSDS_E_1R — GCLK tco 3.152 3.387 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 ns GCLK PLL t co 1.328 1.502 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns RSDS_E_3R — GCLK t co 3.148 3.390 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 ns GCLK PLL t co 1.324 1.505 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns |
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