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AT90USB646 Datasheet(PDF) 141 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 141 Page - ATMEL Corporation |
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141 / 456 page  141 7593L–AVR–09/12 AT90USB64/128 15.10.7 TCNT1H and TCNT1L – Timer/Counter1 15.10.8 TCNT3H and TCNT3L – Timer/Counter3 The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit registers” on page 117. Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com- pare match between TCNTn and one of the OCRnx Registers. Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. 15.10.9 OCR1AH and OCR1AL – Output Compare Register 1 A 15.10.10 OCR1BH and OCR1BL – Output Compare Register 1 B 15.10.11 OCR1CH and OCR1CL – Output Compare Register 1 C Bit 7 65 43 21 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00 00 00 00 Bit 7 65 43 21 0 TCNT3[15:8] TCNT3H TCNT3[7:0] TCNT3L Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00 00 00 00 Bit 7 65 43 21 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00 00 00 00 Bit 7 65 43 21 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00 00 00 00 Bit 7 65 43 21 0 OCR1C[15:8] OCR1CH OCR1C[7:0] OCR1CL Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00 00 00 00 |
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