AT90USB646 datasheet(272/456 Pages) ATMEL

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272

7593L–AVR–09/12

AT90USB64/128

23.16 Overflow

In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if

the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI

interrupt is triggered (if enabled). The packet is acknowledged and the RXOUTI interrupt is also

triggered (if enabled). The bank is filled with the first bytes of the packet.

It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should

write only if the bank is ready to access data (TXINI=1 or RWAL=1).

23.17 Interrupts

Figure 23-8 shows all the interrupts sources.

Figure 23-8. USB device controller interrupt system.

There are two kinds of interrupts: processing (that is, their generation are part of the normal pro-

cessing) and exception (errors).

Processing interrupts are generated when:

• VBUS plug-in detection (insert, remove)(VBUSTI)

• Upstream resume(UPRSMI)

• End of resume(EORSMI)

• Wake up(WAKEUPI)

• End of reset (Speed Initialization)(EORSTI)

• Start of frame(SOFI, if FNCERR=0)

• Suspend detected after 3ms of inactivity(SUSPI)

Exception Interrupts are generated when:

• CRC error in frame number of SOF(SOFI, FNCERR=1)

UPRSMI

UDINT.6

UPRSME

UDIEN.6

EORSMI

UDINT.5

EORSME

UDIEN.5

WAKEUPI

UDINT.4

WAKEUPE

UDIEN.4

EORSTI

UDINT.3

EORSTE

UDIEN.3

SOFI

UDINT.2

SOFE

UDIEN.2

SUSPI

UDINT.0

SUSPE

UDIEN.0

USB device

interrupt

AT90USB646 Datasheet(PDF) 272 Page - ATMEL Corporation

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