AT90USB646 datasheet(269/456 Pages) ATMEL

269 / 456 page

269

7593L–AVR–09/12

AT90USB64/128

RXOUTI shall always be cleared before clearing FIFOCON.

The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can

read data from the bank, and cleared by hardware when the bank is empty.

Figure 23-6. Example with 1 and 2 OUT data bank.

23.13.2

Detailed description

The data are read by the CPU, following the next flow:

• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled

(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending

on the software architecture

• The CPU acknowledges the interrupt by clearing RXOUTI

• The CPU can read the number of byte (N) in the current bank (N=BYCT)

• The CPU can read the data from the current bank (“N” read of UEDATX)

• The CPU can free the bank by clearing FIFOCON when all the data is read, that is:

– after “N” read of UEDATX

– as soon as RWAL is cleared by hardware

If the endpoint uses two banks, the second one can be filled by the HOST while the current one

is being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already

ready and RXOUTI is set immediately.

23.14 IN endpoint management

IN packets are sent by the USB device controller, upon an IN request from the host. All the data

can be written by the CPU, which acknowledge or not the bank when it is full.

OUT

DATA

(to bank 0)

ACK

RXOUTI

FIFOCON

OUT

DATA

(to bank 0)

ACK

read data from CPU

BANK 0

OUT

DATA

(to bank 0)

ACK

RXOUTI

FIFOCON

OUT

DATA

(to bank 1)

ACK

Example with 2 OUT data banks

read data from CPU

BANK 0

read data from CPU

BANK 0

read data from CPU

BANK 1

NAK

AT90USB646 Datasheet(PDF) 269 Page - ATMEL Corporation

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