AD9681 datasheet(7/40 Pages) AD

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Data Sheet

AD9681

Rev. A | Page 7 of 40

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter

1, 2

Symbol

Temp

Min

Typ

Max

Unit

CLOCK3

Input Clock Rate

Full

1000

MHz

Conversion Rate

Full

125

MSPS

Clock Pulse Width High

tEH

Full

4.00

Clock Pulse Width Low

tEL

Full

4.00

OUTPUT PARAMETERS3

Propagation Delay

tPD

Full

1.5

2.3

3.1

Rise Time (20% to 80%)

Full

300

Fall Time (20% to 80%)

Full

300

FCO±1, FCO±2 Propagation Delay

tFCO

Full

1.5

2.3

3.1

DCO±1, DCO±2 Propagation Delay4

tCPD

Full

tFCO + (tSAMPLE/16)

DCO±1, DCO±2 to Data Delay4

tDATA

Full

(tSAMPLE/16) − 300

(tSAMPLE/16)

(tSAMPLE/16) + 300

DCO±1, DCO±2 to FCO±1, FCO±2 Delay4

tFRAME

Full

(tSAMPLE/16) − 300

(tSAMPLE/16)

(tSAMPLE/16) + 300

Lane Delay

tLD

Data to Data Skew

tDATA-MAX − tDATA-MIN

Full

±50

±200

Wake-Up Time (Standby)

25°C

250

Wake-Up Time (Power-Down)5

25°C

375

μs

Pipeline Latency

Full

Clock

cycles

APERTURE

Aperture Delay

25°C

Aperture Uncertainty (Jitter)

25°C

135

fs rms

Out-of-Range Recovery Time

25°C

Clock

cycles

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2 Measured on standard FR-4 material.

3 Adjustable using the SPI. The conversion rate is the clock rate after the divider.

4 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fSAMPLE.

5 Wake-up time is defined as the time required to return to normal operation from power-down mode.

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