AD9681 datasheet(34/40 Pages) AD

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AD9681

Data Sheet

Rev. A | Page 34 of 40

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Interfacing to High Speed ADCs via SPI.

Device Index (Register 0x05)

There are certain features in the map that can be set independently

for each channel, whereas other features apply globally to all

channels (depending on context), regardless of which are selected.

Bits[3:0] in Register 0x05 select which individual data channels

are affected. The output clock channels are selected in Register 0x05

as well. A smaller subset of the independent feature list can be

applied to those devices.

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment

they are written. Setting Bit 0 = 1 in the transfer register initializes

the settings in the ADC resolution/sample rate override register

(Address 0x100).

Power Modes (Register 0x08)

Bits[7:6]—Open

Bit 5—External Power-Down Pin Function

When set (Bit 5 = 1), the external PDWN pin initiates standby

mode. When cleared (Bit 5 = 0), the external PDWN pin

initiates full power-down mode.

Bits[4:2]—Open

Bits[1:0]—Internal Power-Down Mode

In normal operation (Bits[1:0] = 00), all ADC channels are active.

In full power-down mode (Bits[1:0] = 01), the digital datapath

clocks are disabled and the digital datapath is reset. Outputs are

disabled.

In standby mode (Bits[1:0] = 10), the digital datapath clocks

and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), all the digital datapath clocks

and the outputs (where applicable) on the chip are reset, except

the SPI port. Note that the SPI is always left under control of the

user; that is, it is never automatically disabled or in reset (except

by power-on reset).

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

For applications that are sensitive to offset voltages and other

low frequency noise, such as homodyne or direct conversion

receivers, chopping in the first stage of the AD9681 is a feature

that can be enabled by setting Bit 2 = 1. In the frequency domain,

chopping translates offsets and other low frequency noise to

fCLK/2, where they can be filtered.

Bits[1:0]—Open

Output Mode (Register 0x14)

Bit 7—Open

Bit 6—LVDS-ANSI/LVDS-IEEE Option

Setting Bit 6 = 1 chooses the LVDS-IEEE (reduced range) option.

(The default setting is LVDS-ANSI.) As described in Table 18,

when either LVDS-ANSI mode or the LVDS-IEEE reduced range

link is selected, the user can select the driver termination resistor

in Register 0x15, Bits[5:4]. The driver current is automatically

selected to give the proper output swing.

Table 18. LVDS-ANSI/LVDS-IEEE Options

LVDS-ANSI/

LVDS-IEEE

Option, Bit 6

Output

Mode

Output Driver

Termination

Output Driver

Current

LVDS-ANSI

User selectable

Automatically

selected to give

proper swing

LVDS-IEEE

reduced

range link

User selectable

Automatically

selected to give

proper swing

Bits[5:3]—Open

Bit 2—Output Invert

Setting Bit 2 = 1 inverts the output bit stream.

Bit 1—Open

Bit 0—Output Format

By default, setting Bit 0 = 1 sends the data output in twos

complement format. Clearing this bit (Bit 0 = 0) changes the

output mode to offset binary.

Output Adjust (Register 0x15)

Bits[7:6]—Open

Bits[5:4]—Output Driver Termination

These bits allow the user to select the internal output driver

termination resistor.

Bits[3:1]—Open

Bit 0—FCO±x, DCO±x Output Drive

Bit 0 of the output adjust register controls the drive strength on

the LVDS driver of the FCO±1, FCO±2, DCO±1, and DCO±2

outputs only. The default value (Bit 0 = 0) sets the drive to 1×.

Increase the drive to 2× by setting the appropriate channel bit in

used with the output driver termination selected. The termination

selection takes precedence over the 2× driver strength on FCO±1,

FCO±2, DCO±1, and DCO±2 when both the output driver

termination and output drive are selected.

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