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Data Sheet

AD9681

Rev. A | Page 23 of 40

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) that is due only to aperture jitter (tJ) is expressed by

SNR Degradation = 20 log10

















In this equation, the rms aperture jitter represents the root sum

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 47).

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 47. Ideal SNR vs. Input Frequency and Jitter

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9681. Separate the

clock driver power supplies from the ADC output driver supplies

to avoid modulating the clock signal with digital noise. Low jitter,

crystal controlled oscillators are excellent clock sources. If another

type of source generates the clock (by gating, dividing, or another

method), ensure that it is retimed by the original clock at the

last step.

See the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance, and the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter,

for more in depth information about jitter performance as it

relates to ADCs.

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 48, the power dissipated by the AD9681 is

proportional to its sample rate and can be set to one of several

power saving modes using Register 0x100, Bits[2:0].

0.9

0.8

0.7

0.6

0.5

0.4

0.3

130

SAMPLE RATE (MSPS)

110

50MSPS

SETTING

80MSPS

SETTING

125MSPS

SETTING

40MSPS

SETTING

20MSPS

SETTING

65MSPS

SETTING

105MSPS

SETTING

Figure 48. Total Power vs. fSAMPLE for fIN = 9.7 MHz

The AD9681 is placed in power-down mode either by the SPI

port or by asserting the PDWN pin high. In this state, the ADC

typically dissipates 2 mW. During power-down, the output drivers

are placed in a high impedance state. Asserting the PDWN pin

low returns the AD9681 to its normal operating mode. Note

that PDWN is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. The internal capacitors are discharged when the

device enters power-down mode and then must be recharged

when returning to normal operation. As a result, wake-up time

is related to the time spent in power-down mode, and shorter

power-down cycles result in proportionally shorter wake-up

times. When using the SPI port interface, the user can place the

ADC in power-down mode or standby mode. Standby mode

allows the user to keep the internal reference circuitry powered

when faster wake-up times are required. See the Memory Map

section for more details on using these features.

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