AD9681 datasheet(14/40 Pages) AD

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AD9681

Data Sheet

Rev. A | Page 14 of 40

Pin No.

Mnemonic

Description

G12, G11

D0−A1, D0+A1

Lane 0 Bank 1 Digital Output Complement, Lane 0 Bank 1 Digital Output True.

H12, H11

D1−A1, D1+A1

Lane 1 Bank 1 Digital Output Complement, Lane 1 Bank 1 Digital Output True.

J12, J11

D0−A2, D0+A2

Lane 0 Bank 2 Digital Output Complement, Lane 0 Bank 2 Digital Output True.

K12, K11

D1−A2, D1+A2

Lane 1 Bank 2 Digital Output Complement, Lane 1 Bank 2 Digital Output True.

L12, L11

D0−B1, D0+B1

Lane 0 Bank 1 Digital Output Complement, Lane 0 Bank 1 Digital Output True.

M12, M11

D1−B1, D1+B1

Lane 1 Bank 1 Digital Output Complement, Lane 1 Bank 1 Digital Output True.

M10, L10

D0−B2, D0+B2

Lane 0 Bank 2 Digital Output Complement, Lane 0 Bank 2 Digital Output True.

M9, L9

D1−B2, D1+B2

Lane 1 Bank 2 Digital Output Complement, Lane 1 Bank 2 Digital Output True.

M4, L4

D0−C1, D0+C1

Lane 0 Bank 1 Digital Output Complement, Lane 0 Bank 1 Digital Output True.

M3, L3

D1−C1, D1+C1

Lane 1 Bank 1 Digital Output Complement, Lane 1 Bank 1 Digital Output True.

M1, M2

D0−C2, D0+C2

Lane 0 Bank 2 Digital Output Complement, Lane 0 Bank 2 Digital Output True.

L1, L2

D1−C2, D1+C2

Lane 1 Bank 2 Digital Output Complement, Lane 1 Bank 2 Digital Output True.

K1, K2

D0−D1, D0+D1

Lane 0 Bank 1 Digital Output Complement, Lane 0 Bank 1 Digital Output True.

J1, J2

D1−D1, D1+D1

Lane 1 Bank 1 Digital Output Complement, Lane 1 Bank 1 Digital Output True.

H1, H2

D0−D2, D0+D2

Lane 0 Bank 2 Digital Output Complement, Lane 0 Bank 2 Digital Output True.

G1, G2

D1−D2, D1+D2

Lane 1 Bank 2 Digital Output Complement, Lane 1 Bank 2 Digital Output True.

M6, L6;

M7, L7

DCO−1, DCO+1;

DCO−2, DCO+2

Data Clock Digital Output Complement, Data Clock Digital Output True. DCO±1 is used to

capture D0±x1/D1±x1 digital output data, and DCO±2 is used to capture D0±x2/D1±x2 digital

output data.

M5, L5;

M8, L8

FCO−1, FCO+1;

FCO−2, FCO+2

Frame Clock Digital Output Complement, Frame Clock Digital Output True. FCO±1 frames

D0±x1/D1±x1 digital output data, and FCO±2 frames D0±x2/D1±x2 digital output data.

F12

SCLK/DTP

Serial Clock/Digital Test Pattern.

F11

SDIO/OLM

Serial Data Input/Output/Output Lane Mode.

E10, F10

CSB1, CSB2

Chip Select Bar. CSB1 enables/disables the SPI for four channels in Bank 1; CSB2 enables/

disables the SPI for four channels in Bank 2.

G10

PDWN

Power-Down.

E12, E11

VIN−A1, VIN+A1