| Electronic Components Datasheet Search |
|
AD9681 Datasheet(PDF) 25 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9681 Datasheet(HTML) 25 Page - Analog Devices |
|
25 / 40 page ![]() Data Sheet AD9681 Rev. A | Page 25 of 40 Figure 51 shows an example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on standard FR-4 material. Figure 52 shows an example of trace lengths exceeding 24 inches on standard FR-4 material. Note that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. 6k 7k 1k 2k 3k 5k 4k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps 500 400 300 200 100 –500 –400 –300 –200 –100 0 –0.8ns –0.4ns 0ns 0.4ns 0.8ns EYE: ALL BITS ULS: 7000/400354 Figure 51. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4 Material, External 100 Ω Far End Termination Only It is the responsibility of the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all eight outputs to drive longer trace lengths, which can be achieved by program- ming Register 0x15. Although this option produces sharper rise and fall times on the data edges and is less prone to bit errors, it also increases the power dissipation of the DRVDD supply. 500 400 300 200 100 –500 –400 –300 –200 –100 0 –0.8ns –0.4ns 0ns 0.4ns –0.8ns EYE: ALL BITS ULS: 8000/414024 10k 12k 2k 4k 6k 8k 0k –800ps –600ps –400ps –200ps 0ps 200ps 400ps 600ps Figure 52. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater Than 24 Inches on Standard FR-4 Material, External 100 Ω Far End Termination Only The default format of the output data is twos complement. Table 10 shows an example of the output coding format. To change the output data format to offset binary, see the Memory Map section, Register 0x14, Bit[0]. Table 10. Digital Output Coding Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode VIN+ − VIN− <−VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000 VIN+ − VIN− −VREF 0000 0000 0000 0000 1000 0000 0000 0000 VIN+ − VIN− 0 V 1000 0000 0000 0000 0000 0000 0000 0000 VIN+ − VIN− +VREF − 1.0 LSB 1111 1111 1111 1100 0111 1111 1111 1100 VIN+ − VIN− >+VREF − 0.5 LSB 1111 1111 1111 1100 0111 1111 1111 1100 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |