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AS3911 Datasheet(PDF) 89 Page - ams AG |
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AS3911 Datasheet(HTML) 89 Page - ams AG |
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89 / 149 page  ams Datasheet, Confidential: 2013-Oct [2-03] AS3911 – 89 Appl icatio n I n f o rm a t i o n FIFO Status Register 2 Figure 75: FIFO Status Register 2 Note(s) and/or Footnote(s): 1. At power-up and after direct commands Set Default and Clear, content of this register is set to 0. 2. If FIFO is empty, the value of register FIFO Status Register 1 (0x1Ah) is 0x00, register bits fifo_ncp, fifo_lb2, fifo_lb1 and fifo_lb0 in register block 0x1Bh are cleared. Correct procedure for FIFO read is to read both "FIFO Status Register 1 & 2" and then read FIFO. Second register values need to be saved in MCU, if non-complete bytes are in FIFO. Address 1Bh: FIFO Status Register 2 Type: R Bit Name Default Function Comments 7 6fifo_unf FIFO underflow Set when more bytes then actual content of FIFO were read 5 fifo_ovr FIFO overflow 4 fifo_ncp Last FIFO byte is not complete 3fifo_lb2 Number of bits in last FIFO byte in case it was not complete (fifo_npc=1) In case of incomplete byte the LSB part is valid 2fifo_lb1 1fifo_lb0 0 np_lb Parity bit is missing in last byte This is a framing error |
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