AS3911 datasheet(34/149 Pages) AMSCO

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AS3911 – 34

ams Datasheet, Confidential: 2013-Oct [2-03]

A p pl i c at io n I n f o r m at i o n

is useful to detect the moment when the peer NFC device (it

can be either an initiator or a target) has stopped emitting an

RF field.

The External Field Detector is automatically enabled in the low

power Peer Detection mode when NFCIP-1 mode (initiator or

target) is selected in the Bit Rate Definition Register.

Additionally it can be enabled by setting bit en_fd in the

Auxiliary Definition Register.

Collision Avoidance Threshold

This threshold is used during the RF Collision Avoidance

sequence which is executed by sending NFC Field ON

commands (see “NFC Field ON Commands” on page 51). It can

be selected in the range from 25 mVpp to 800 mVpp.

Power Supply System

The AS3911 features two positive supply pins, VDD and VDD_IO.

VDD is the main power supply pin. It supplies the AS3911 blocks

through three regulators (VDD_A, VDD_D and VDD_RF). VDD range

from 2.4 to 5.5V is supported.

VDD_IO is used to define supply level for digital communication

pins (/SS, MISO, MOSI, SCLK, IRQ, MCU_CLK). Digital

communication pins interface to the AS3911 logic through level

shifters, therefore the internal supply voltage can be either

higher or lower than VDD_IO. VDD_IO range from 1.65V to 5.5V is

supported.

Figure 19 shows the building blocks of the AS3911 power

supply system. It contains three regulators, a power-down

support block, a block generating analog reference voltage

(AGD) and a block performing automatic power supply

adjustment procedure. The three regulators are providing

supply to analog blocks (VSP_A), logic (VSP_D) and transmitter

(VSP_RF). The use of VSP_A and VSP_D regulators is mandatory

at 5V power supply to provide regulated voltage to analog and

logic blocks which only use 3.3V devices. The use of VSP_A and

VSP_D regulators at 3V supply and VSP_RF regulator at any

supply voltage is recommended to improve system PSRR.

Regulated voltage can be adjusted automatically to have

maximum possible regulated voltage while still having good

PSRR. All regulator pins also have corresponding negative

supply pins which are externally connected to ground potential

(VSS). The reason for separation is in decoupling of noise

induced by voltage drops on the internal power supply lines.

Figure 10 and Figure 11 depict typical AS3911 application

schematics with all regulators used. All regulator pins and AGD

voltage are buffered with pairs of ceramic and electrolyte. For

regulators recommended blocking capacitors values can be

found in the table below are 2.2μF in parallel with 10nF, for pin

AGD 1μF in parallel with 10nF is suggested.

AS3911 Datasheet(PDF) 34 Page - ams AG

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