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AS3911 Datasheet(PDF) 45 Page - ams AG

Part # AS3911
Description  NFC Initiator / HF Reader IC
PDF  149 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3911 Datasheet(HTML) 45 Page - ams AG

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ams Datasheet, Confidential: 2013-Oct [2-03]
AS3911 – 45
Appl icatio n I n f o rm a t i o n
Figure 32:
SPI Read Timing
Interrupt Interface
There are three interrupt registers implemented in the AS3911
(Main Interrupt Register and auxiliary Timer and NFC Interrupt
Register and Error and Wake-up Interrupt Register). Main
Interrupt Register contains information about six interrupt
sources, while two bits reference to interrupt sources detailed
in Timer and NFC Interrupt Register and Error and Wake-up
Interrupt Register.
When an interrupt condition is met the source of interrupt bit
is set in the Main Interrupt Register and the IRQ pin transitions
to high.
The microcontroller then reads the Main Interrupt Register to
distinguish between different interrupt sources. In case the bits
pointing to auxiliary Interrupt register are set, additionally
corresponding auxiliary interrupt register(s) has to be read.
After a particular Interrupt Register is read, its content is reset
to 0. Exceptions to this rule are the bits pointing to auxiliary
registers. These bits are only cleared when corresponding
auxiliary register is read. IRQ pin transitions to low after the
interrupt bit(s) which caused its transition to high has been
read. Please note that there may be more than one interrupt
bits set in case the microcontroller did not immediately read
the interrupt registers after the IRQ signal was set and another
event causing interrupt occurred. In that case the IRQ pin
transitions to low after the last bit which caused interrupt is
read.
In case an interrupt from a certain source is not required it can
be disabled by setting corresponding bit in the Mask Interrupt
registers. In case of masking a certain interrupt source the
interrupt is not produced, but the source of interrupt bit is still
set in interrupt registers.
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