AS3911 datasheet(46/149 Pages) AMSCO

46 / 149 page

AS3911 – 46

ams Datasheet, Confidential: 2013-Oct [2-03]

A p pl i c at io n I n f o r m at i o n

Figure 33:

IRQ Output

FIFO Water Level and FIFO Status Registers

The AS3911 contains a 96 byte FIFO. In case of transmitting the

Control logic shifts the data, which was previously loaded by

the external microcontroller to the Framing Block and further

to the Transmitter. During reception, the demodulated data is

stored in the FIFO and the external microcontroller can

download received data once reception was terminated.

Transmit and receive capabilities of the AS3911 are not limited

by the FIFO size due to a FIFO water level interrupt system.

During transmission an interrupt is sent (IRQ due to FIFO water

level in the Main Interrupt Register) when the content of data

in the FIFO passes from (water level + 1) to water level and the

complete transmit frame has not been loaded in the FIFO yet.

The external microcontroller can now add more data in the FIFO.

The same stands for the reception: when the number of

received bytes passes from (water level - 1) to water level an

interrupt is sent to inform the external controller that data has

to be downloaded from FIFO in order not to lose receive data

due to FIFO overflow.

During transmission water level IRQ is additionally set in case

all transmission bytes have not been written in FIFO yet and if

number of bytes written into FIFIO is lower than water level. In

this case an IRQ is sent when number of bytes in FIFO drops

below 4.

It is important to note that FIFO IRQ is not produced while SPI

is active in FIFO load or read mode. Due to this the FIFO

loading/reading rate has to be higher than Tx/Rx bit rate, once

FIFO loading/reading is finished the /SS pin has to be pulled to

VDD (logic remains in FIFO load/read mode as long as /SS

remains low).

In case controller knows that the receive data frame is smaller

than the FIFO size the water level interrupt does not have to be

served. In such case the water level interrupt can be masked.

The external controller has to serve the FIFO faster than data is

transmitted or received. Using SCLK frequency which is at least

double than the actual receive or transmit bit rate is

recommended.

There are two settings of the FIFO water level available for

receive and transmit in the IO Configuration Register 1.

After data reception is terminated the external microcontroller

needs to know how much data is still stored in the FIFO: This

information is available in the FIFO Status Register 1 and FIFO

Status Register 2 which displays number of bytes in the FIFO

Name

Signal

Signal Level

Description

IRQ

Digital output

CMOS

Interrupt output pin

AS3911 Datasheet(PDF) 46 Page - ams AG

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