AFE032 datasheet(33/77 Pages) TI1

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AFE032

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SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

DSP Path State Retention

By default, blocks 1 through 4 of the DSP path retain their states in between DAC sample bursts (when DAC

mode is deasserted). This default implementation functions best for most applications provided that all DAC

sample bursts end with at least 24 samples of midrange values. These 24 samples provide a smooth transition to

SPI mode. The default implementation can be altered by changing the DSP_CFG bit of the REG_AUX_CTL

DAC Sample Clipping and Bias

The device provides the ability to clip DAC samples at the last stage of digital processing. An additional offset

may be added to the clipped DAC sample at the user's discretion. The clipping circuit operates in the following

manner:

•

Program the device with an 11-bit clip value on the REG_CLIP0 and REG_CLIP1 registers.

•

Program the device with an 11-bit clip offset value on the REG_CLIP_OFFSET0 and REG_CLIP_OFFSET1

registers.

•

The programmed clip and offset values are not signed.

•

The device digital logic compares the 11-bit magnitude of the DAC sample from the DSP path to the clip

value.

•

If the magnitude of the DAC sample is greater than the clip value, then the final DAC sample equals the clip

value minus the offset value.

•

If the magnitude of the DAC sample is less than the clip value, then the final DAC sample is unchanged.

AFE032 Reset Options

The device has two main types of reset mechanisms available. These reset options are hardware invoked and

software invoked.

External Reset and Analog Shutdown Mode

The device can be disabled by asserting the external SD pin. Asserting the external SD pin causes the device

digital logic to reset and also causes the analog module to shut down. Asserting the external SD pin disables the

DAC clock and the entire device is disabled. Adhere to the following protocol when asserting the external SD pin:

•

Assert the SD pin for at least 1 µs.

•

Make sure that the device receives a valid XCLK clock before, during, and after the SD pin is asserted.

When the SD pin is deasserted, a valid XCLK signal must be sent to the device for at least 65,536 cycles. The

device must be reprogrammed because all control registers are now reset.

Software Reset Options

Two types of software resets can be applied to the device digital logic: soft reset and sticky reset. Soft reset and

sticky reset create a reset pulse that is eight DAC_CLK cycles wide for the internal logic. These two reset

commands are controlled by the REG_AFE032_CTL register. Sticky reset preserves all SPI register settings. In

order to properly use the sticky reset, the values of all other control bits in the REG_AFE032_CTL register must

be read and noted before asserting the sticky reset bit. Whatever is written to the REG_AFE032_CTL register is

latched when performing a sticky reset. A soft reset, on the other hand, brings all device digital circuits to their

default states.

After a soft reset or sticky reset is performed, a valid XCLK signal must be sent to the device for at least 65,536

cycles. The device must be reprogrammed because all control registers are now reset (with the exception of the

REG_AFE032_CTL register bits in the case of a sticky reset).

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