AFE032 datasheet(51/77 Pages) TI1

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AFE032

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SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

Table 36. REG_CLIP_OFFSET_1 Register (Address = 17h)

CLIP_OFF_LSB

Reserved

R/W

LEGEND: R/W = read and write; R = read-only.

Bits[7:5]

CLIP_OFF_LSB

These bits are the LSB of the 11-bit clip offset value. Clipped DAC Samples have this offset subtracted from the

clipped value.

These bits control DAC_CLIP_OFF[2:0].

Default = 0

Bits[4:0]

Reserved

These bits are reserved.

Default = 0

Table 37. REG_AUX_CTL Register (Address = 18h)

Reserved

DSP_CFG

Reserved

R/W

LEGEND: R/W = read and write; R = read-only.

Bits[7:6]

Reserved

This bits are reserved.

Default = 0

Bit 5

DSP_CFG

This bit allows the state of the DSP blocks to be retained or to be forced to their reset values during SPI mode.

0 = Hold the state of the DSP path blocks when the device is in SPI mode (default)

1 = Reset the state of the DSP path when the device is in DAC mode

Bits[4:1]

Reserved

These bits are reserved.

Default = 3h

Bit 0

Reserved

This bit is reserved.

Default = 0

Table 38. RESERVED Registers (Address = 19h to 23h)

Reserved

LEGEND: R = read-only.

These registers are reserved.

Table 39. REG_COEFF1_BLOCK_2_MS Register (Address = 24h)

Bits 11:4 of coefficient 1 for filter block 2

R/W

LEGEND: R/W = read and write.

Bits [7:0]

Bits 11:4 of coefficient 1 for filter block 2

These bits contain the eight most significant bits of coefficient 1 for filter block 2.

Default = B9h

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