AFE032 datasheet(49/77 Pages) TI1

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AFE032

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SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

Table 28. REG_CLK_DIV Register (Address = 0Fh)

DAC clock POST_CLK_DIV

DAC clock PRE_CLK_DIV

R/W

LEGEND: R/W = read and write.

Bits[7:4]

DAC clock POST_CLK_DIV

Internal DAC clock divider offset.

These bits control the value of the second clock divider. DAC_CLK is related to XCLK by: XCLK = (PRE_CLK_DIV

+ 1) × (POST_CLK_DEV + 1) x DAC_CLK.

Default = 0

Bits[3:0]

DAC clock PRE_CLK_DIV

Internal DAC clock divider offset.

These bits control the value of the first clock divider. DAC_CLK is related to XCLK by: XCLK = (PRE_CLK_DIV + 1)

× (POST_CLK_DEV + 1) x DAC_CLK.

Default = 3h

Table 29. REG_OFFSET_0 Register (Address = 10h)

Most significant byte of block 4 parameter

R/W

LEGEND: R/W = read and write.

Bits[7:0]

Most significant byte of block 4 parameter

These bits are the MSB of the 32-bit parameter for block 4 of the DSP path.

Default = F5h

Table 30. REG_OFFSET_1 Register (Address = 11h)

Second to MSB of block 4 parameter

R/W

LEGEND: R/W = read and write.

Bits[7:0]

Second to MSB of block 4 parameter

These bits are second in line to the MSB of the block 4 parameter.

Default = C2h

Table 31. REG_OFFSET_2 Register (Address = 12h)

Third to MSB of block 4 parameter

R/W

LEGEND: R/W = read and write.

Bits[7:0]

Third to MSB of block 4 parameter

These bits are third in line to the MSB of the block 4 parameter.

Default = 8Fh

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