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THS4524MDBTREP Datasheet(PDF) 4 Page - National Semiconductor (TI)

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Part # THS4524MDBTREP
Description  VERY LOW POWER, NEGATIVE RAIL INPUT, RAIL-TO-RAIL OUTPUT,FULLY DIFFERENTIAL AMPLIFIER
PDF  48 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

THS4524MDBTREP Datasheet(HTML) 4 Page - National Semiconductor (TI)

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THS4524-EP
SBOS609A – JUNE 2012 – REVISED AUGUST 2013
www.ti.com
THERMAL INFORMATION
THS4524
THERMAL METRIC(1)
DBT
UNITS
38 PINS
θJA
Junction-to-ambient thermal resistance(2)
106.9
θJCtop
Junction-to-case (top) thermal resistance(3)
59.8
θJB
Junction-to-board thermal resistance(4)
66.5
°C/W
ψJT
Junction-to-top characterization parameter(5)
17.1
ψJB
Junction-to-board characterization parameter(6)
66.1
θJCbot
Junction-to-case (bottom) thermal resistance(7)
N/A
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3.3 V
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, and input and output referenced to midsupply, unless otherwise noted.
TA = -55°C to 125°C
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
AC PERFORMANCE
Small-Signal Bandwidth
VOUT = 100 mVPP, G = 1
135
MHz
C
VOUT = 100 mVPP, G = 2
49
MHz
C
VOUT = 100 mVPP, G = 5
18.6
MHz
C
VOUT = 100 mVPP, G = 10
9.3
MHz
C
Gain Bandwidth Product
VOUT = 100 mVPP, G = 10
93
MHz
C
Large-Signal Bandwidth
VOUT = 2 VPP, G = 1
95
MHz
C
Bandwidth for 0.1-dB Flatness
VOUT = 2 VPP, G = 1
20
MHz
C
Rising Slew Rate (Differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
420
V/
μs
C
Falling Slew Rate (Differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
460
V/
μs
C
Overshoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
1.2
%
C
Undershoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
2.1
%
C
Rise Time
VOUT = 2-V Step, G = 1, RL = 200 Ω
4
ns
C
Fall Time
VOUT = 2-V Step, G = 1, RL = 200 Ω
3.5
ns
C
Settling Time to 1%
VOUT = 2-V Step, G = 1, RL = 200 Ω
13
ns
C
Harmonic Distortion
f = 1 kHz, VOUT = 1 VRMS, G = 1
(2),
2nd harmonic
–122
dBc
C
differential input
f = 1 MHz, VOUT = 2 VPP, G = 1
–85
dBc
C
f = 1 kHz, VOUT = 1 VRMS, G = 1
(2),
3rd harmonic
–141
dBc
C
differential input
f = 1 MHz, VOUT = 2 VPP, G = 1
–90
dBc
C
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
Second-Order Intermodulation Distortion
–83
dBc
C
VOUT = 2-VPP envelope
(1)
Test levels: (A) 100% tested. (B) Limits set by characterization and simulation. (C) Typical value only for information.
(2)
Not directly measureable; calculated using noise gain of 101 as described in the Applications section, Audio Performance.
4
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