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EM73P982 Datasheet(PDF) 20 Page - ELAN Microelectronics Corp |
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EM73P982 Datasheet(HTML) 20 Page - ELAN Microelectronics Corp |
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20 / 41 page ![]() 20 * This specification are subject to be changed without notice. EM73P982 EM73P982 EM73P982 EM73P982 EM73P982 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 12.25.2001 EI : Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when inter- rupt happened, EI is cleared to "0" automatically, after RTI instruction happened, EI will be set to "1" again. Priority checker: Check interrupt priority when multiple interrupts happened. INTERRUPT FUNCTION INTERRUPT FUNCTION INTERRUPT FUNCTION INTERRUPT FUNCTION INTERRUPT FUNCTION The procedure of interrupt operation: 1. Push PC and all flags to stack. 2. Set interrupt entry address into PC. 3. Set SF= 1. 4. Clear EI to inhibit other interrupts happened. 5. Clear the IL for which interrupt source has already be accepted. 6. To excute interrupt subroutine from the interrupt entry address. 7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests. PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA" LDIA #1100B; EXAE; set mask register "1100B" EICIL 111111B ; enable interrupt F.F. POWER SAVING FUNCTION ( Sleep / Hold functlon ) POWER SAVING FUNCTION ( Sleep / Hold functlon ) POWER SAVING FUNCTION ( Sleep / Hold functlon ) POWER SAVING FUNCTION ( Sleep / Hold functlon ) POWER SAVING FUNCTION ( Sleep / Hold functlon ) During sleep and hold condition, CPU holds the system's internal status with a low power consumption, for the sleep mode, the system clock will be stoped in the sleep condition and system need a warm up time for the stability of system clock running after wakeup. In the other way, for the hold mode, the system clock does not stop at all and it does not need a warm-up time any way. The sleep and hold mode is controlled by Port 16 and released by P0(0..3)/WAKEUP0..3 or P8(0..3)/ WAKEUPA..D. Sleep and hold condition: 1. Osc stop (sleep only) and CPU internal status held. 2. Internal time base clear to "0". P16 3 2 1 0 initial value :0000 SWWT Set wake-up warm-up time 2 /XIN 2 /XIN 2 /XIN Hold mode SE Enable sleep/hold 0 Reserved 1 Enable sleep / hold rnode 0 1 Wake-up in edge release mode Wake-up in level release mode 0 0 0 1 1 0 1 1 18 14 16 WM SE SWWT WM Set wake-up release mode 3. CPU internal memory, flags, register, I/O held original states. 4. Program counter hold the executed address after sleep release. Release condition: 1. Osc start to oscillating (sleep only). 2. Warm-up time passing (sleep only). 3. According PC to execute the following program. |
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