EM73P982 datasheet(19/41 Pages) EMC

19 / 41 page

* This specification are subject to be changed without notice.

EM73P982

4-BIT MICROCONTROLLER

12.25.2001

For the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as

external timer/counter input (P8.1/TRGB, P8.3/TRGA), interrupt request will be generated as soon as

timer/counter count overflow.

Internal pulse

TimerB(TimerA) value

n+1

n+2

n+3

n+4

n+5

P8.1/TRGB(P8.3/TRGA)

PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode.

LDIA #1100b;

OUTA P28; Enable timerA with pulse width measurement mode.

INTERRUPT FUNCTION

There are 5 interrupt sources, 1 external interrupt sources, 4 internal interrupt sources. Multiple

interrupts are admitted according the priority.

Type

Interrupt source

Priority

Interrupt

Program ROM

Latch

Enable condition

entry address

External

Externalinterrupt(INT0)

IL5

EI=1

002h

Internal

Reserved

IL4

EI=1,MASK3=1

004h

Internal

TimerA overflow interrupt (TRGA)

IL3

EI=1,MASK2=1

006h

Internal

TimerB overflow interrupt (TRGB)

IL2

EI=1,MASK1=1

008h

Internal

Time base interrupt(TBI)

IL1

00Ah

Internal

Speech ending interrupt (SPI)

IL0

EI=1,MASK0=1

00Ch

INTERRUPT STRUCTURE

Interrupt controller:

IL0-IL5

: Interrupt latch. Hold all interrupt requests from all interrupt sources. ILr can not be

set by program, but can be reset by program or system reset, so IL only can decide

which interrupt source can be accepted.

MASK0-MASK3

: Except INT0, MASK register can promit or inhibit all interrupt sources.

MASK0 MASK1 MASK1 MASK2 MASK3

IL0

IL1

TBI

Reset by system reset and program

instruction

IL2

IL3

TRGA

IL4

IL5

INT0

Priority checker

Entry address generator

Interrupt request

Interrupt entry address

Reset by system reset and program

instruction

Set by program instruction

by EICIL or DICIL

TRGB

SPI

Reserved

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