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EM73P982 Datasheet(PDF) 21 Page - ELAN Microelectronics Corp |
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EM73P982 Datasheet(HTML) 21 Page - ELAN Microelectronics Corp |
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21 / 41 page  21 * This specification are subject to be changed without notice. EM73P982 EM73P982 EM73P982 EM73P982 EM73P982 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 12.25.2001 There is only one kind of sleep/hold release mode. 1. Edge release mode: Release sleep/hold condition by the falling edge of any one of P0(0..3)/WAKEUP0..3 or P8(0..3)/ WAKEUPA..D. Note : There are 8 independent mask options for wakeup function in EM73P982. So, the wakeup function of P0(0..3)/WAKEUP0..3 and P8(0..3)/WAKEUPA..D are enabled or disabled independently. LCD DRIVER LCD DRIVER LCD DRIVER LCD DRIVER LCD DRIVER It can directly drive the liquid crystal display ( LCD ) and has 40 segments, 8 commons output pins. There are total 40x8 dots can be display. The VRLC pin is the LCD driver power input, there is the voltage of ( Vcc - VRLC ) to LCD. (1) LCD driver control command register: Port27 3210 Initial value: 0h LDC LDC LDC LDC LDC * * * * * * * * * * LCD DISPLAY CONTROL LCD DISPLAY CONTROL LCD DISPLAY CONTROL LCD DISPLAY CONTROL LCD DISPLAY CONTROL LDC Function description 0 0 LCD display disable 0 1 Blanking, change COMMON pin output 1 0 Reserved 1 1 LCD display enable * : Don't care. P27 is the LDC driver control command register. The initial value is 0000. When LDC ( bit2 and bit3 of P27 ) is set to "0000", the LCD display is disabled. When LDC is set to "0010", the LCD is blanking, the COM pins are inactive and the SEG pins continuously output the display data. The power switch of LCD driver is turned off when the CPU is reseted. When LDC is set to "0110", the LCD display is enabled, the power switch is turned on and it can not be turned off forever except the CPU is reseted again. The power switch is also turned off during the sleep operation. Users must enable the LCD display again by self when the CPU is waked up. (2) LCD display data area: (2) LCD display data area: (2) LCD display data area: (2) LCD display data area: (2) LCD display data area: The LCD display data is stored in the display data area of the data memory (RAM). The display data area begins with address 20H during reset. The LCD display data area is as below: CO M 0 CO M 1 CO M 2 CO M 3 CO M 4 CO M 5 CO M 6 CO M 7 20H 30H 40H 50H 60H 70H 80H 90H b i t 0 b i t 1 b i t 2 b i t 3 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 1 0 S E G 1 1 S E G 1 2 S E G 1 3 S E G 1 4 S E G 1 5 S E G 1 6 S E G 1 7 S E G 1 8 S E G 1 9 S E G 2 0 S E G 2 1 S E G 2 2 S E G 2 3 S E G 2 4 S E G 2 5 S E G 2 6 S E G 2 7 S E G 2 8 S E G 2 9 S E G 3 0 S E G 3 1 S E G 3 2 S E G 3 3 S E G 3 4 S E G 3 5 S E G 3 6 S E G 3 7 S E G 3 8 S E G 3 9 0 1 2 3456 789 A B C D E F RAM |
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