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EM73P982 Datasheet(PDF) 16 Page - ELAN Microelectronics Corp |
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EM73P982 Datasheet(HTML) 16 Page - ELAN Microelectronics Corp |
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16 / 41 page ![]() 16 * This specification are subject to be changed without notice. EM73P982 EM73P982 EM73P982 EM73P982 EM73P982 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 4-BIT MICROCONTROLLER 12.25.2001 TIME BASE INTERRUPT (TBI ) TIME BASE INTERRUPT (TBI ) TIME BASE INTERRUPT (TBI ) TIME BASE INTERRUPT (TBI ) TIME BASE INTERRUPT (TBI ) The time base can be used to generate a fixed frequency interrupt. There are 8 kinds of frequencies can be selected by setting "P25" Single clock mode P25 3 2 1 0 ( initial value 0000 ) 0 0 x x: Interrupt disable 0 1 0 0: Interrupt frequency XIN / 210 Hz 0 1 0 1: Interrupt frequency XIN / 211 Hz 0 1 1 0: Interrupt frequency XIN / 212 Hz 0 1 1 1: Interrupt frequency XIN / 213 Hz 1 1 0 0: Interrupt frequency XIN / 29 Hz 1 1 0 1: Interrupt frequency XIN / 28 Hz 1 1 1 0: Interrupt frequency XIN / 215 Hz 1 1 1 1: Interrupt frequency XIN / 217 Hz 1 0 x x: Reserved TIMER / COUNTER ( TIMERA, TIMERB) TIMER / COUNTER ( TIMERA, TIMERB) TIMER / COUNTER ( TIMERA, TIMERB) TIMER / COUNTER ( TIMERA, TIMERB) TIMER / COUNTER ( TIMERA, TIMERB) Timer/counters can support user three special functions: 1. Even counter 2. Timer. 3. Pulse-width measurement. These three functions can be executed by 2 timer/counter independently. For timerA, the counter data is saved in timer register TAH, TAM, TAL, which user can set counter initial value and read the counter value by instruction "LDATAH(M,L), STATAH(M,L)" and timer register is TBH, TBM, TBL and W/R instruction "LDATBH (M,L), STATBH (M,L)". The basic structure of timer/counter is composed by two same structure counter, these two counters can be set initial value and send counter value to timer register, P28 and P29 are the command ports for timerA and timer B, user can choose different operation mode and different internal clock rate by setting these two ports. When timer/counter overflow, it will generate a TRGA(B) interrupt request to interrupt control unit. To access TA, TB, user must switch RAM at bank0. |
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