LP3971 datasheet(5/57 Pages) TI1

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LP3971

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SNVS432U – JANUARY 2006 – REVISED OCTOBER 2008

Pin Functions

Pin Descriptions

Pin #

Name

I/O

Type

Description

PWR_ON

This is an active HI push button input which can be used to signal PWR_ON

and PWR_OFF events to the CPU by controlling the ext_wakup [pin4] and

select contents of register 8H'02

nTEST_JIG

This is an active LOW input signal used for detecting an external HW event. The

response is seen in the ext_wakup [pin4] and select contents of register 8H'02

SPARE

This is an input signal used for detecting a external HW event. The response is

seen in the ext_wakup [pin4] and select contents of register 8H'02. The polarity

on this pin is assignable

EXT_WAKEUP

This pin generates a single 10mS pulse output to CPU in response to input from

pin[s] 1, 2, and 3. Flags CPU to interrogate register 8H'02

FB1

Buck1 input feedback terminal

VIN

PWR

Battery Input (Internal circuitry and LDO1-3 power input)

VOUT LDO1

PWR

LDO1 output

VOUT LDO2

PWR

LDO2 output

nRSTI

Active low Reset pin. Signal used to reset the IC (by default is pulled high

internally). Typically a push button reset.

GND1

Ground

VREF

Bypass Cap. for the high internal impedance reference.

VOUT LDO3

PWR

LDO3 output

VOUT LDO4

PWR

LDO4 output

VIN LDO4

PWR

Power input to LDO4, this can be connected to either from a 1.8V supply to

main Battery supply.

VIN BUBATT

PWR

Back Up Battery input supply.

VOUT LDO_RTC

PWR

LDO_RTC output supply to the RTC of the application processor.

nBATT_FLT

Main Battery fault output, indicates the main battery is low

(discharged) or the dc source has been removed from the system. This gives

the processor an indicator that the power will shut down. During this time the

processor will operate from the back up coin cell.

PGND2

Buck2 NMOS Power Ground

SW2

PWR

Buck2 switcher output

VIN Buck2

PWR

Battery input power to Buck2

SDA

I/O

I2C Data (Bidirectional)

SCL

I2C Clock

FB2

Buck2 input feedback terminal

nRSTO

Reset output from the PMIC to the processor

VOUT LDO5

PWR

LDO5 output

VIN LDO5

PWR

Power input to LDO5, this can be connected to VIN or to a separate 1.8V supply.

VDDA

PWR

Analog Power for VREF, BIAS

FB3

Buck3 Feedback

GPIO1 /

I/O

General Purpose I/O / Ext. backup battery charger enable pin. This pin enables

nCHG_EN

the main battery / DC source power to charge the backup battery. This pin

toggled via the application processor. By grounding this pin the DC source

continuously charges the backup battery

GPIO2

I/O

General Purpose I/O

VIN Buck3

PWR

Battery input power to Buck3

SW3

PWR

Buck3 switcher output

PGND3

Buck3 NMOS Power Ground

BGND1,2,3

Bucks 1, 2 and 3 analog Ground

SYNC

Frequency Synchronization: Connection to an external clock signal PLL to

synchronize the PMIC internal oscillator.

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